fenpin.vhd

李同宇 彩灯控制 vhdl 用于实验过程的理解

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity fenpin IS
 port( clk,clr: in std_logic;
       clk0,clk1,clk2,clk3,clk4:buffer std_logic);
end fenpin;
ARCHITECTURE arch OF fenpin IS
signal cnter0:integer range 0 to 6000;
signal cnter1,cnter2,cnter3,cnter4:integer range 0 to 10;
begin
process(clk,clr)--10khz
begin
if   clr='1' then 
     cnter0<=0;
elsif  clk'event and clk='1' then 
     if cnter0=4999 then 
        cnter0<=0; clk0<='1'; 
     else  cnter0<=cnter0+1;clk0<='0';
     end if;
end if;
end process;
process(clk0,clr)--1khz
begin
if   clr='1' then 
    cnter1<=0;
elsif  clk0'event and clk0='1' then 
     if cnter1=9 then 
        cnter1<=0; clk1<='1'; 
     else  cnter1<=cnter1+1;clk1<='0';
     end if;
end if;
end process;
process(clk1,clr)--100hz
begin
if   clr='1' then 
    cnter2<=0;
elsif  clk1'event and clk1='1' then 
     if cnter2=9 then 
        cnter2<=0; clk2<='1'; 
     else  cnter2<=cnter2+1;clk2<='0';
     end if;
end if;
end process;
process(clk2,clr)--10hz
begin
if   clr='1' then 
    cnter3<=0;
elsif  clk2'event and clk2='1' then 
     if cnter3=9 then 
        cnter3<=0; clk3<='1';
     else  cnter3<=cnter3+1;clk3<='0'; 
     end if;
end if;
end process;
process(clk3,clr)--1hz
begin
if   clr='1' then 
    cnter4<=0;
elsif  clk3'event and clk3='1' then 
     if cnter4=9 then 
        cnter4<=0; clk4<='1';
     else  cnter4<=cnter4+1;clk4<='0'; 
     end if;
end if;
end process;
END arch;