📄 start167.lst
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0000 356 _RDYEN1 EQU 0 ; 0 = READY# function disabled
357 ; ; 1 = READY# function enabled
358 ;
359 ; RDY_AS1: Synchronous / Asynchronous READY# Input (BUSCON1.3):
360 ; Note: This bit is only valid if _RDYEN1 == 1.
0000 361 _RDY_AS1 EQU 0 ; 0 = synchronous READY# input
362 ; ; 1 = asynchronous READY# input
363 ;
364 ; CSREN1: Read Chip Select Enable bit (BUSCON1.14):
0000 365 _CSREN1 EQU 0 ; 0 = CS1# is independent of read command (RD#)
366 ; ; 1 = CS1# is generated for the duration of read
367 ;
368 ; CSWEN1: Write Chip Select Enable bit (BUSCON1.15):
0000 369 _CSWEN1 EQU 0 ; 0 = CS1# is independent of write command (WR#)
370 ; ; 1 = CS1# is generated for the duration of write
371 ;
372 ;
373 ; BUSCON2/ADDRSEL2
374 ; --- Set BUSCON2 = 1 to initialize the BUSCON2/ADDRSEL2 registers
375 $SET (BUSCON2 = 0)
376 ;
377 ; Define the start address and the address range of Chip Select 2 (CS2#)
378 ; This values are used to set the ADDRSEL2 register
379 ; Set CS2# Start Address (default 200000H)
380 ; Set CS2# Range (default 1024K = 1MB)
381 ;
382 ; MCTC2: Memory Cycle Time (BUSCON2.0 .. BUSCON2.3):
383 ; Note: if RDYEN2 == 1 a maximum number of 7 waitstates can be selected
0001 384 _MCTC2 EQU 1 ; Memory wait states is 1 (MCTC2 field = 0EH).
385 ;
386 ; RWDC2: Read/Write Signal Delay (BUSCON2.4):
0000 387 _RWDC2 EQU 0 ; 0 = Delay Time 0.5 States
388 ; ; 1 = No Delay Time 0 States
A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 7
389 ;
390 ; MTTC2: Memory Tri-state Time (BUSCON2.5):
0001 391 _MTTC2 EQU 1 ; 0 = Delay Time 0.5 States
392 ; ; 1 = No Delay Time 0 States
393 ;
394 ; BTYP2: External Bus Configuration Control (BUSCON2.6 .. BUSCON2.7):
0002 395 _BTYP2 EQU 2 ; 0 = 8 Bit Non Multiplexed
396 ; ; 1 = 8 Bit Multiplexed
397 ; ; 2 = 16 Bit Non Multiplexed
398 ; ; 3 = 16 Bit Multiplexed
399 ;
400 ; ALECTL2: ALE Lengthening Control Bit (BUSCON2.9):
0000 401 _ALECTL2 EQU 0 ; see data sheet for description
402 ;
403 ; BUSACT2: Bus Active Control Bit (BUSCON2.10):
0001 404 _BUSACT2 EQU 1 ; = 0 external (ADDRSEL2) bus disabled
405 ; = 1 external (ADDRSEL2) bus enabled
406 ;
407 ; RDYEN2: READY# Input Enable control bit (BUSCON2.12):
0000 408 _RDYEN2 EQU 0 ; 0 = READY# function disabled
409 ; ; 1 = READY# function enabled
410 ;
411 ; RDY_AS2: Synchronous / Asynchronous READY# Input (BUSCON2.3):
412 ; Note: This bit is only valid if _RDYEN2 == 1.
0000 413 _RDY_AS2 EQU 0 ; 0 = synchronous READY# input
414 ; ; 1 = asynchronous READY# input
415 ;
416 ; CSREN2: Read Chip Select Enable bit (BUSCON2.14):
0000 417 _CSREN2 EQU 0 ; 0 = CS2# is independent of read command (RD#)
418 ; ; 1 = CS2# is generated for the duration of read
419 ;
420 ; CSWEN2: Write Chip Select Enable bit (BUSCON2.15):
0000 421 _CSWEN2 EQU 0 ; 0 = CS2# is independent of write command (WR#)
422 ; ; 1 = CS2# is generated for the duration of write
423 ;
424 ;
425 ; BUSCON3/ADDRSEL3
426 ; --- Set BUSCON3 = 1 to initialize the BUSCON3/ADDRSEL3 registers
427 $SET (BUSCON3 = 0)
428 ;
429 ; Define the start address and the address range of Chip Select 3 (CS3#)
430 ; This values are used to set the ADDRSEL3 register
431 ; Set CS3# Start Address (default 300000H)
432 ; Set CS3# Range (default 1024K = 1MB)
433 ;
434 ; MCTC3: Memory Cycle Time (BUSCON3.0 .. BUSCON3.3):
435 ; Note: if RDYEN3 == 1 a maximum number of 7 waitstates can be selected
0001 436 _MCTC3 EQU 1 ; Memory wait states is 1 (MCTC3 field = 0EH).
437 ;
438 ; RWDC3: Read/Write Signal Delay (BUSCON3.4):
0000 439 _RWDC3 EQU 0 ; 0 = Delay Time 0.5 States
440 ; ; 1 = No Delay Time 0 States
441 ;
442 ; MTTC3: Memory Tri-state Time (BUSCON3.5):
0001 443 _MTTC3 EQU 1 ; 0 = Delay Time 0.5 States
444 ; ; 1 = No Delay Time 0 States
445 ;
446 ; BTYP3: External Bus Configuration Control (BUSCON3.6 .. BUSCON3.7):
0002 447 _BTYP3 EQU 2 ; 0 = 8 Bit Non Multiplexed
448 ; ; 1 = 8 Bit Multiplexed
449 ; ; 2 = 16 Bit Non Multiplexed
450 ; ; 3 = 16 Bit Multiplexed
451 ;
452 ; ALECTL3: ALE Lengthening Control Bit (BUSCON3.9):
0000 453 _ALECTL3 EQU 0 ; see data sheet for description
454 ;
A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 8
455 ; BUSACT3: Bus Active Control Bit (BUSCON3.10):
0001 456 _BUSACT3 EQU 1 ; = 0 external (ADDRSEL3) bus disabled
457 ; = 1 external (ADDRSEL3) bus enabled
458 ;
459 ; RDYEN3: READY# Input Enable control bit (BUSCON3.12):
0000 460 _RDYEN3 EQU 0 ; 0 = READY# function disabled
461 ; ; 1 = READY# function enabled
462 ;
463 ; RDY_AS3: Synchronous / Asynchronous READY# Input (BUSCON3.3):
464 ; Note: This bit is only valid if _RDYEN3 == 1.
0000 465 _RDY_AS3 EQU 0 ; 0 = synchronous READY# input
466 ; ; 1 = asynchronous READY# input
467 ;
468 ; CSREN3: Read Chip Select Enable bit (BUSCON3.14):
0000 469 _CSREN3 EQU 0 ; 0 = CS3# is independent of read command (RD#)
470 ; ; 1 = CS3# is generated for the duration of read
471 ;
472 ; CSWEN3: Write Chip Select Enable bit (BUSCON3.15):
0000 473 _CSWEN3 EQU 0 ; 0 = CS3# is independent of write command (WR#)
474 ; ; 1 = CS3# is generated for the duration of write
475 ;
476 ;
477 ; BUSCON4/ADDRSEL4
478 ; --- Set BUSCON4 = 1 to initialize the BUSCON4/ADDRSEL4 registers
479 $SET (BUSCON4 = 0)
480 ;
481 ; Define the start address and the address range of Chip Select 4 (CS4#)
482 ; This values are used to set the ADDRSEL4 register
483 ; Set CS4# Start Address (default 400000H)
484 ; Set CS4# Range (default 1024K = 1MB)
485 ;
486 ; MCTC4: Memory Cycle Time (BUSCON4.0 .. BUSCON4.3):
487 ; Note: if RDYEN4 == 1 a maximum number of 7 waitstates can be selected
0001 488 _MCTC4 EQU 1 ; Memory wait states is 1 (MCTC4 field = 0EH).
489 ;
490 ; RWDC4: Read/Write Signal Delay (BUSCON4.4):
0000 491 _RWDC4 EQU 0 ; 0 = Delay Time 0.5 States
492 ; ; 1 = No Delay Time 0 States
493 ;
494 ; MTTC4: Memory Tri-state Time (BUSCON4.5):
0001 495 _MTTC4 EQU 1 ; 0 = Delay Time 0.5 States
496 ; ; 1 = No Delay Time 0 States
497 ;
498 ; BTYP4: External Bus Configuration Control (BUSCON4.6 .. BUSCON4.7):
0002 499 _BTYP4 EQU 2 ; 0 = 8 Bit Non Multiplexed
500 ; ; 1 = 8 Bit Multiplexed
501 ; ; 2 = 16 Bit Non Multiplexed
502 ; ; 3 = 16 Bit Multiplexed
503 ;
504 ; ALECTL4: ALE Lengthening Control Bit (BUSCON4.9):
0000 505 _ALECTL4 EQU 0 ; see data sheet for description
506 ;
507 ; BUSACT4: Bus Active Control Bit (BUSCON4.10):
0001 508 _BUSACT4 EQU 1 ; = 0 external (ADDRSEL4) bus disabled
509 ; = 1 external (ADDRSEL4) bus enabled
510 ;
511 ; RDYEN4: READY# Input Enable control bit (BUSCON4.12):
0000 512 _RDYEN4 EQU 0 ; 0 = READY# function disabled
513 ; ; 1 = READY# function enabled
514 ;
515 ; RDY_AS4: Synchronous / Asynchronous READY# Input (BUSCON4.3):
516 ; Note: This bit is only valid if _RDYEN4 == 1.
0000 517 _RDY_AS4 EQU 0 ; 0 = synchronous READY# input
518 ; ; 1 = asynchronous READY# input
519 ;
520 ; CSREN4: Read Chip Select Enable bit (BUSCON4.14):
A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 9
0000 521 _CSREN4 EQU 0 ; 0 = CS4# is independent of read command (RD#)
522 ; ; 1 = CS4# is generated for the duration of read
523 ;
524 ; CSWEN4: Write Chip Select Enable bit (BUSCON4.15):
0000 525 _CSWEN4 EQU 0 ; 0 = CS4# is independent of write command (WR#)
526 ; ; 1 = CS4# is generated for the duration of write
527 ;
528 ;------------------------------------------------------------------------------
529
$IF TINY
$SET (DPPUSE = 0)
532 $ENDIF
533
0000 534 _STKSZ SET 0
0000 535 _STKSZ1 SET 0 ; size is 512 Words
536 $IF (STK_SIZE = 0)
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