📄 start167.lst
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175 ;
176 ; WATCHDOG: Disable Hardware Watchdog
177 ; --- Set WATCHDOG = 1 to enable the Hardware watchdog
178 $SET (WATCHDOG = 1)
179 ;
180 ;
181 ; CLR_MEMORY: Disable Memory Zero Initialization of RAM area
182 ; --- Set CLR_MEMORY = 0 to disable memory zero initilization
183 $SET (CLR_MEMORY = 1)
184 ;
185 ; INIT_VARS: Disable Variable Initialization
186 ; --- Set INIT_VARS = 0 to disable variable initilization
187 $SET (INIT_VARS = 1)
188 ;
189 ; DPPUSE: Re-assign DPP registers
190 ; --- Set DPPUSE = 0 to reduce the code size of the startup code, if you
A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 4
191 ; are not using the L166 DPPUSE directive.
192 $SET (DPPUSE = 1)
193 ;
194 ; DPP3USE: Use DPP3 register during variable initilization
195 ; --- Set DPP3USE = 0 to disable the usage of DPP3 during initilization of
196 ; variables. This option might be required if you write
197 ; program parts that are reloaded during application
198 ; execution and increase code size of the startup code.
199 $SET (DPP3USE = 1)
200 ;
201 ;------------------------------------------------------------------------------
202 ; Initialization for XPERCON register (available on some derivatives only)
203 ;
204 ; INIT_XPERCON: Init XPERCON register available on some devices
205 ; --- Set INIT_XPERCON = 1 to initilize the XPERCON register
206 $SET (INIT_XPERCON = 0)
207 ;
208 ; Note: The verious devices of 166/ST10 family provide different XPERCON
209 ; registers. Therefore you can set a fixed XPERCON value with the
210 ; following EQU statment. Please consult the Microcontroller
211 ; User's Guide for the exact definition of the XPERCON SFR in your
212 ; 166/ST10 derivative.
213 ;
214 ; Bit 15 11 7 3
0000 215 V_XPERCON EQU 0000$0000$0000$0000B ; XPERCON values
216 ;
217 ; XPERCON Bits in various devices (Note: not all devices are listed)
218 ; C165UTAH: Bit 5: IOM-2, Bit 6: USB, Bit 7: EPEC
219 ; C167CS: Bit 0: CAN1, Bit 1: CAN2, Bit 10: XRAM 2K Bit 11: XRAM 6K
220 ;
221 ;------------------------------------------------------------------------------
222 ;
223 ; Initialization for SYSCON2 and SYSCON3 (available on some derivatives only)
224 ; Note: The SYSCON2 and SYSCON3 bits may be different in some derivatives.
225 ; Check the values carefully!
226 ;
227 ; ADVANCED_SYSCON: Init SYSCON2 and SYSCON3 register available on some devices
228 ; --- Set ADVANCE_SYSCON = 1 to initilize SYSCON2 and SYSCON3
229 $SET (ADVANCED_SYSCON = 0)
230 ;
231 ; --- SYSCON2 values
232 ;
233 ; PDCON: Power Down Control (during power down mode) (SYSCON2.4 .. SYSCON2.5)
0000 234 PDCON EQU 0 ; 0 = RTC On, Ports On (default after Reset)
235 ; ; 1 = RTC On, Ports Off
236 ; ; 2 = RTC Off, Ports On
237 ; ; 3 = RTC Off, Ports Off
238 ;
239 ; RTS: RTC Clock Source (not affected by a reset) (SYSCON2.6)
0000 240 RTS EQU 0 ; 0 = Main oscillator
241 ; ; 1 = Auxiliary oscillator (if available)
242 ;
243 ; SCS: SDD Clock Source (not affected by a reset) (SYSCON2.7)
0000 244 SCS EQU 0 ; 0 = Main oscillator
245 ; ; 1 = Auxiliary oscillator (if available)
246 ;
247 ; CLKCON: Clock State Control (SYSCON2.8 .. SYSCON2.9)
0000 248 CLKCON EQU 0 ; 0 = Running on configured basic frequency
249 ; ; 1 = Running on slow down frequency, PLL ON
250 ; ; 2 = Running on slow down frequency, PLL OFF
251 ; ; 3 = reserved
252 ;
253 ; CLKREL: Reload Counter Value for Slowdown Devider (SYSCON2.10 .. SYSCON2.14)
0000 254 CLKREL EQU 0 ; possible values are 0 .. 31
255 ;
256 ;
A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 5
257 ; --- SYSCON3 values: disable on-chip peripherals
258 ;
0000 259 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0)
0000 260 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1)
0000 261 SSCDIS EQU 0 ; 1 = disable Synchronus Serial Cnl SSC (SYSCON3.2)
0000 262 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3)
263 ; reserved (SYSCON3.4)
0000 264 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
0000 265 CC1DIS EQU 0 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6)
0000 266 CC2DIS EQU 0 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7)
0000 267 CC6DIS EQU 0 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8)
0000 268 PWMDIS EQU 0 ; 1 = disable Pulse Width Modulation Unit (SYSCON3.9)
0000 269 ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10)
0000 270 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11)
271 ; ; reserved (SYSCON3.12)
0000 272 CAN1DIS EQU 0 ; 1 = disable on-chip CAN Module 1 (SYSCON3.13)
0000 273 CAN2DIS EQU 0 ; 1 = disable on-chip CAN Module 2 (SYSCON3.14)
0000 274 PCDDIS EQU 0 ; 1 = disable Peripheral Clock Driver (SYSCON3.15)
275 ;
276 ;------------------------------------------------------------------------------
277 ; Initialization for RSTCON register (available on some derivatives only)
278 ;
279 ; INIT_RSTCON: Init RSTCON register available on some devices
280 ; --- Set INIT_RSTCON = 1 to initilize the RSTCON register
281 $SET (INIT_RSTCON = 0)
282 ;
283 ; --- RSTCON values
284 ;
285 ; R_RSTLEN: Reset Length Control (duration of next reset; RSTCON.0 .. RSTCON.1)
0000 286 R_RSTLEN EQU 0 ; 0 = 1024 TCL: standard duration
287 ; ; 1 = 2048 TCL: extended duration
288 ;
289 ; R_SUE: Software Update enable (RSTCON.8)
0000 290 R_SUE EQU 0 ; 0 = Configuration cannot be changed (default)
291 ; ; 1 = Software update of configuration is enabled
292 ;
293 ; R_CSSEL: Chip Select Lines (number of CS pins; RSTCON.9 .. RSTCON.10)
0000 294 R_CSSEL EQU 0 ; 0 = 3 CS lines (CS2# .. CS0#) (default)
295 ; ; 1 = 2 CS lines (CS1# .. CS0#)
296 ; ; 2 = No CS lines at all
297 ; ; 3 = all CS lines (CSx# .. CS0#)
298 ;
299 ; R_SALSEL: Segment Address Lines (number of address pins; RSTCON.11 .. RSTCON.12)
0000 300 R_SALSEL EQU 0 ; 0 = 4-bit segment address: A19 .. A16 (default)
301 ; ; 1 = No segment address lines at all
302 ; ; 2 = full segment address: Axx .. A16
303 ; ; 3 = 2-bit segment address: A17 .. A16
304 ;
305 ; R_CLKCFG: Clock Generation Mode (XTAL PLL factor; RSTCON.13 .. RSTCON.15)
0000 306 R_CLKCFG EQU 0 ; 0 = CPU CLOCK = XTAL * 2.5
307 ; ; 1 = CPU CLOCK = XTAL / 2.0
308 ; ; 2 = CPU CLOCK = XTAL * 1.5
309 ; ; 3 = CPU CLOCK = XTAL (direct drive)
310 ; ; 4 = CPU CLOCK = XTAL * 5.0
311 ; ; 5 = CPU CLOCK = XTAL * 2.0
312 ; ; 6 = CPU CLOCK = XTAL * 3.0
313 ; ; 7 = CPU CLOCK = XTAL * 4.0
314 ;
315 ;------------------------------------------------------------------------------
316 ;
317 ; BUSCON1/ADDRSEL1 .. BUSCON4/ADDRSEL4 Initialization
318 ; ===================================================
319 ;
320 ;
321 ; BUSCON1/ADDRSEL1
322 ; --- Set BUSCON1 = 1 to initialize the BUSCON1/ADDRSEL1 registers
A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 6
323 $SET (BUSCON1 = 0)
324 ;
325 ; Define the start address and the address range of Chip Select 1 (CS1#)
326 ; This values are used to set the ADDRSEL1 register
327 ; Set CS1# Start Address (default 100000H)
328 ; Set CS1# Range (default 1024K = 1MB)
329 ;
330 ; MCTC1: Memory Cycle Time (BUSCON1.0 .. BUSCON1.3):
331 ; Note: if RDYEN1 == 1 a maximum number of 7 waitstates can be selected
0001 332 _MCTC1 EQU 1 ; Memory wait states is 1 (MCTC1 field = 0EH).
333 ;
334 ; RWDC1: Read/Write Signal Delay (BUSCON1.4):
0000 335 _RWDC1 EQU 0 ; 0 = Delay Time 0.5 States
336 ; ; 1 = No Delay Time 0 States
337 ;
338 ; MTTC1: Memory Tri-state Time (BUSCON1.5):
0001 339 _MTTC1 EQU 1 ; 0 = Delay Time 0.5 States
340 ; ; 1 = No Delay Time 0 States
341 ;
342 ; BTYP1: External Bus Configuration Control (BUSCON1.6 .. BUSCON1.7):
0002 343 _BTYP1 EQU 2 ; 0 = 8 Bit Non Multiplexed
344 ; ; 1 = 8 Bit Multiplexed
345 ; ; 2 = 16 Bit Non Multiplexed
346 ; ; 3 = 16 Bit Multiplexed
347 ;
348 ; ALECTL1: ALE Lengthening Control Bit (BUSCON1.9):
0000 349 _ALECTL1 EQU 0 ; see data sheet for description
350 ;
351 ; BUSACT1: Bus Active Control Bit (BUSCON1.10):
0001 352 _BUSACT1 EQU 1 ; = 0 external (ADDRSEL1) bus disabled
353 ; = 1 external (ADDRSEL1) bus enabled
354 ;
355 ; RDYEN1: READY# Input Enable control bit (BUSCON1.12):
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