📄 start167.lst
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A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 1
MACRO ASSEMBLER A166 V4.22
OBJECT MODULE PLACED IN START167.OBJ
ASSEMBLER INVOKED BY: C:\Keil\C166\BIN\A166.EXE START167.A66 SEGMENTED MOD167 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 $MOD167 ; Define C167 mode
2 ;
3 ;------------------------------------------------------------------------------
4 ; This file is part of the C166 Compiler package
5 ; Copyright KEIL ELEKTRONIK GmbH 1993 - 2001
6 ; Version 4.12
7 ;------------------------------------------------------------------------------
8 ; START167.A66: This code is executed after processor reset and provides the
9 ; startup sequence for the extended 166 architecture CPU's.
10 ; (i.e. C167/C165/C164/C163/C161, ST10-262 ect.)
11 ;
12 ; To translate this file use A166 with the following invocation:
13 ;
14 ; A166 START167.A66 SET (<model>)
15 ;
16 ; <model> determines the memory model and can be one of the following:
17 ; TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE or HLARGE
18 ;
19 ; Example: A166 START167.A66 SET (SMALL)
20 ;
21 ; To link the modified START167.OBJ file to your application use the following
22 ; L166 invocation:
23 ;
24 ; L166 <your object file list>, START167.OBJ <controls>
25 ;
26 ;------------------------------------------------------------------------------
27 ; Setup model-dependend Assembler controls
28 $CASE
29 $IF NOT TINY
30 $SEGMENTED
31 $ENDIF
32 ;------------------------------------------------------------------------------
33 ;
34 ; Definitions for BUSCON0 and SYSCON Register:
35 ; --------------------------------------------
36 ;
37 ; MCTC0: Memory Cycle Time (BUSCON0.0 .. BUSCON0.3):
38 ; Note: if RDYEN0 == 1 a maximum number of 7 waitstates can be selected
0001 39 _MCTC0 EQU 1 ; Memory wait states is 1 (MCTC0 field = 0EH).
40 ; ; (Reset Value = 15 additional state times)
41 ;
42 ; RWDC0: Read/Write Signal Delay (BUSCON0.4):
0000 43 _RWDC0 EQU 0 ; 0 = Delay Time 0.5 States (Reset Value)
44 ; ; 1 = No Delay Time 0 States
45 ;
46 ; MTTC0: Memory Tri-state Time (BUSCON0.5):
0001 47 _MTTC0 EQU 1 ; 0 = Delay Time 0.5 States (Reset Value)
48 ; ; 1 = No Delay Time 0 States
49 ;
50 $SET (BTYP_ENABLE = 0) ; 0 = BTYP0 and BUSACT0 is set according to the level
51 ; at pins P0L.6, P0L.7, and EA# during reset.
52 ; 1 = the following _BTYP0 and _BUSACT0 values are
53 ; written to BTYP0 and BUSACT0
54 ;
55 ; BTYP0: External Bus Configuration Control (BUSCON0.6 .. BUSCON0.7):
0002 56 _BTYP0 EQU 2 ; 0 = 8 Bit Non Multiplexed
57 ; ; 1 = 8 Bit Multiplexed
58 ; ; 2 = 16 Bit Non Multiplexed
A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 2
59 ; ; 3 = 16 Bit Multiplexed
60 ;
61 ; ALECTL0: ALE Lengthening Control Bit (BUSCON0.9):
0000 62 _ALECTL0 EQU 0 ; see data sheet for description
63 ;
64 ; BUSACT0: Bus Active Control Bit (BUSCON0.10):
0001 65 _BUSACT0 EQU 1 ; = 0 external bus disabled
66 ; = 1 external bus enabled
67 ;
68 ; RDYEN0: READY# Input Enable control bit (BUSCON0.12):
0000 69 _RDYEN0 EQU 0 ; 0 = READY# function disabled (Reset Value)
70 ; ; 1 = READY# function enabled
71 ;
72 ; RDY_AS0: Synchronous / Asynchronous READY# Input (BUSCON0.3):
73 ; Note: This bit is only valid if _RDYEN0 == 1.
0000 74 _RDY_AS0 EQU 0 ; 0 = synchronous READY# input
75 ; ; 1 = asynchronous READY# input
76 ;
77 ; CSREN0: Read Chip Select Enable bit (BUSCON0.14, only in some devices):
0000 78 _CSREN0 EQU 0 ; 0 = CS0# is independent of read command (RD#)
79 ; ; 1 = CS0# is generated for the duration of read
80 ;
81 ; CSWEN0: Write Chip Select Enable bit (BUSCON0.15, only in some devices):
0000 82 _CSWEN0 EQU 0 ; 0 = CS0# is independent of write command (WR#)
83 ; ; 1 = CS0# is generated for the duration of write
84 ;
85 ; XPERSHARE: XBUS Peripheral Share Mode Control (SYSCON.0)
0000 86 _XPERSHARE EQU 0 ; 0 = External accesses to XBUS peripherals disabled
87 ; ; 1 = XBUS accessible via external BUS in hold mode
88 ;
89 ; VISIBLE: Visible Mode Control (SYSCON.1)
0000 90 _VISIBLE EQU 0 ; 0 = Accesses to XBUS are done internally
91 ; ; 1 = XBUS accesses are made visible on external pins
92 ;
93 ; XPEN: XRAM & XBUS Peripheral Enable Control Bit (SYSCON.2)
0000 94 _XPEN EQU 0 ; 0 = access to on-chip XRAM & XBUS disable => EXT.BUS
95 ; ; 1 = on-chip XRAM & XBUS is accessed
96 ;
97 ; BDRSTEN: Bidirectional Reset Enable Bit (SYSCON.3, only in some devices)
0000 98 _BDRSTEN EQU 0 ; 0 = Pin RSTIN# is an input only
99 ; ; 1 = RSTIN# is pulled low during internal reset
100 ;
101 $SET (OWDDIS_ENABLE = 0); 0 = OWDDIS is set according to the inverted level
102 ; ; at pin RD\ duirng reset.
103 ; ; 1 = the following _OWDDIS value is
104 ; ; written to OWDDIS in the SYSCON register
105 ; OWDDIS: Oscillator Watchdog Disable Bit (SYSCON.4, only in some devices)
0000 106 _OWDDIS EQU 0 ; 0 = the on-chip oscillator watchdog is enabled
107 ; ; 1 = the on-chip oscillator watchdog is disabled
108 ;
109 ; PWDCFG: Power Down Mode Configuration Bit (SYSCON.5, only in some devices)
0000 110 _PWDCFG EQU 0 ; 0 = Power Down mode can be left via reset
111 ; ; 1 = Power Down mode left via ext. or RTC interrupt
112 ;
113 ; CSCFG: Chip Select Configuration Control (SYSCON.6, only in some devices)
0000 114 _CSCFG EQU 0 ; 0 = Latched CS mode; CS signals are latch internally
115 ; ; 1 = Unlatched CS mode
116 ;
117 $SET (WRCFG_ENABLE = 0) ; 0 = WRCFG is set according to the level at
118 ; ; pin P0H.0 during reset.
119 ; ; 1 = the following _WRCFG value is
120 ; ; written to WRCFG in the SYSCON register
121 ; WRCFG: Write Configuration Control Bit (SYSCON.7):
0000 122 _WRCFG EQU 0 ; 0 = Normal configuration of WR# and BHE#
123 ; ; 1 = WR# pin acts as WRL#, BHE# pin acts as WRH#
124 ;
A166 MACRO ASSEMBLER START167 07/02/2002 18:27:53 PAGE 3
125 ; CLKEN: System Clock Output Enable bit (SYSCON.8):
0000 126 _CLKEN EQU 0 ; 0 = disabled (Reset Value)
127 ; ; 1 = enabled
128 ;
129 ; BYTDIS: Byte High Enable pin control bit (SYSCON.9):
0000 130 _BYTDIS EQU 0 ; 0 = enabled (Reset Value)
131 ; ; 1 = disabled
132 ;
133 $SET (ROMEN_ENABLE = 0) ; 0 = ROMEN is set according to the level at
134 ; ; pin EA# during reset.
135 ; ; 1 = the following _ROMEN value is
136 ; ; written to ROMEN in the SYSCON register
137 ; ROMEN: Internal ROM Access Enable control bit (SYSCON.10):
0000 138 _ROMEN EQU 0 ; 0 = Internal ROM disabled
139 ; 1 = Internal ROM enabled
140 ;
141 ; SGTDIS: Segmentation Disable control bit (SYSCON.11):
$IF TINY
_SGTDIS EQU 1 ; disable segmented mode for TINY model
144 $ELSE
0000 145 _SGTDIS EQU 0 ; enable segmented mode (Reset Value)
146 $ENDIF
147 ;
148 ; ROMS1: ROM Segment Mapping Control Bit (SYSCON.12):
0000 149 _ROMS1 EQU 0 ; _ROMS1 = 0 Internal ROM mapped to segment 0
150 ; ; _ROMS1 = 1 Internal ROM mapped to segment 1
151 ;
152 ; STKSZ: Maximum System Stack Size selection (SYSCON.13 .. SYSCON.15)
153 ; Defines the system stack space which is used by CALL/RET and PUSH/POP
154 ; instructions. The system stack space must be adjusted according the
155 ; actual requirements of the application.
156 $SET (STK_SIZE = 0)
157 ; System stack sizes:
158 ; 0 = 256 words (Reset Value)
159 ; 1 = 128 words
160 ; 2 = 64 words
161 ; 3 = 32 words
162 ; 4 = 512 words
163 ; 5 = not implemented
164 ; 6 = not implemented
165 ; 7 = no wrapping (entire internal RAM use as STACK, set size with SYSSZ)
166 ; If you have selected 7 for STK_SIZE, you can set the actual system stack size
167 ; with the following SSTSZ statement.
0200 168 SSTSZ EQU 200H ; set System Stack Size to 200H Bytes
169 ;
170 ; USTSZ: User Stack Size Definition
171 ; Defines the user stack space available for automatics. This stack space is
172 ; accessed by R0. The user stack space must be adjusted according the actual
173 ; requirements of the application.
1000 174 USTSZ EQU 1000H ; set User Stack Size to 1000H Bytes.
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