📄 lpregs.h
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// single flag bits & multi-bit-field masks
#define ACK_EN 0x80
#define FRC_END_STATE 0x20
#define END_STATE_MSK 0x1C
#define ACK_TO_MSK 0x03
// END_STATE field values
#define END_STATE_SLEEP 0x00
#define END_STATE_IDLE 0x04
#define END_STATE_TXSYNTH 0x08
#define END_STATE_RXSYNTH 0x0C
#define END_STATE_RX 0x10
// ACK_TO field values
#define ACK_TO_4X 0x00
#define ACK_TO_8X 0x01
#define ACK_TO_12X 0x02
#define ACK_TO_15X 0x03
// -------------------------------
// Framing Configuration register
// -------------------------------
#define FRAMING_CFG_ADR 0x10
#define FRAMING_CFG_RST 0xA5
// single flag bits & multi-bit-field masks
#define SOP_EN 0x80
#define SOP_LEN 0x40
#define LEN_EN 0x20
#define SOP_THRESH_MSK 0x1F
// -------------------------------
// Data Threshold 32 register
// -------------------------------
#define DATA32_THOLD_ADR 0x11
#define DAT32_THRESH_RST 0x04
#define DAT32_THRESH_MSK 0x0F
// -------------------------------
// Data Threshold 64 register
// -------------------------------
#define DATA64_THOLD_ADR 0x12
#define DAT64_THRESH_RST 0x0A
#define DAT64_THRESH_MSK 0x1F
// -------------------------------
// RSSI register
// -------------------------------
#define RSSI_ADR 0x13
#define RSSI_RST 0x20
// single flag bits & multi-bit-field masks
#define SOP_RSSI 0x80
#define LNA_STATE 0x20
#define RSSI_LVL_MSK 0x1F
// -------------------------------
// EOP Control register
// -------------------------------
#define EOP_CTRL_ADR 0x14
#define EOP_CTRL_RST 0xA4
// single flag bits & multi-bit-field masks
#define HINT_EN 0x80
#define HINT_EOP_MSK 0x70
#define EOP_MSK 0x0F
// -------------------------------
// CRC Seed registers
// -------------------------------
#define CRC_SEED_LSB_ADR 0x15
#define CRC_SEED_MSB_ADR 0x16
#define CRC_SEED_LSB_RST 0x00
#define CRC_SEED_MSB_RST 0x00
// CRC related values
// USB CRC-16
#define CRC_POLY_MSB 0x80
#define CRC_POLY_LSB 0x05
#define CRC_RESI_MSB 0x80
#define CRC_RESI_LSB 0x0D
// -------------------------------
// TX CRC Calculated registers
// -------------------------------
#define TX_CRC_LSB_ADR 0x17
#define TX_CRC_MSB_ADR 0x18
// -------------------------------
// RX CRC Field registers
// -------------------------------
#define RX_CRC_LSB_ADR 0x19
#define RX_CRC_MSB_ADR 0x1A
#define RX_CRC_LSB_RST 0xFF
#define RX_CRC_MSB_RST 0xFF
// -------------------------------
// Synth Offset registers
// -------------------------------
#define TX_OFFSET_LSB_ADR 0x1B
#define TX_OFFSET_MSB_ADR 0x1C
#define TX_OFFSET_LSB_RST 0x00
#define TX_OFFSET_MSB_RST 0x00
// single flag bits & multi-bit-field masks
#define STRIM_MSB_MSK 0x0F
#define STRIM_LSB_MSK 0xFF
// -------------------------------
// Mode Override register
// -------------------------------
#define MODE_OVERRIDE_ADR 0x1D
#define MODE_OVERRIDE_RST 0x00
#define FRC_AWAKE 0x03
#define FRC_AWAKE_OFF_1 0x01
#define FRC_AWAKE_OFF_2 0x00
// single flag bits & multi-bit-field masks
#define DIS_AUTO_SEN 0x80
#define SEN_TXRXB 0x40
#define FRC_SEN 0x20
#define FRC_AWAKE_MSK 0x18
#define MODE_OVRD_FRC_AWAKE 0x18
#define MODE_OVRD_FRC_AWAKE_OFF_1 0x08
#define MODE_OVRD_FRC_AWAKE_OFF_2 0x00
#define RST 0x01
#define FRC_PA 0x02
// -------------------------------
// RX Override register
// -------------------------------
#define RX_OVERRIDE_ADR 0x1E
#define RX_OVERRIDE_RST 0x00
// single flag bits & multi-bit-field masks
#define ACK_RX 0x80
#define EXTEND_RX_TX 0x40
#define MAN_RXACK 0x20
#define FRC_RXDR 0x10
#define DIS_CRC0 0x08
#define DIS_RXCRC 0x04
#define ACE 0x02
// -------------------------------
// TX Override register
// -------------------------------
#define TX_OVERRIDE_ADR 0x1F
#define TX_OVERRIDE_RST 0x00
// single flag bits & multi-bit-field masks
#define ACK_TX_SEN 0x80
#define FRC_PREAMBLE 0x40
#define DIS_TX_RETRANS 0x20
#define MAN_TXACK 0x10
#define OVRRD_ACK 0x08
#define DIS_TXCRC 0x04
#define CO 0x02
#define TXINV 0x01
//------------------------------------------------------------------------------
// File Function Detail
//------------------------------------------------------------------------------
// -------------------------------
// TX Buffer - 16 bytes
// -------------------------------
#define TX_BUFFER_ADR 0x20
// -------------------------------
// RX Buffer - 16 bytes
// -------------------------------
#define RX_BUFFER_ADR 0x21
// -------------------------------
// Framing Code - 8 bytes
// -------------------------------
#define SOP_CODE_ADR 0x22
// CODESTORE_REG_SOF_RST 64'h17_ff_9e_21_36_90_c7_82
#define CODESTORE_BYTE7_SOF_RST 0x17
#define CODESTORE_BYTE6_SOF_RST 0xFF
#define CODESTORE_BYTE5_SOF_RST 0x9E
#define CODESTORE_BYTE4_SOF_RST 0x21
#define CODESTORE_BYTE3_SOF_RST 0x36
#define CODESTORE_BYTE2_SOF_RST 0x90
#define CODESTORE_BYTE1_SOF_RST 0xC7
#define CODESTORE_BYTE0_SOF_RST 0x82
// -------------------------------
// Data Code - 16 bytes
// -------------------------------
#define DATA_CODE_ADR 0x23
// CODESTORE_REG_DCODE0_RST 64'h01_2B_F1_DB_01_32_BE_6F
#define CODESTORE_BYTE7_DCODE0_RST 0x01
#define CODESTORE_BYTE6_DCODE0_RST 0x2B
#define CODESTORE_BYTE5_DCODE0_RST 0xF1
#define CODESTORE_BYTE4_DCODE0_RST 0xDB
#define CODESTORE_BYTE3_DCODE0_RST 0x01
#define CODESTORE_BYTE2_DCODE0_RST 0x32
#define CODESTORE_BYTE1_DCODE0_RST 0xBE
#define CODESTORE_BYTE0_DCODE0_RST 0x6F
// CODESTORE_REG_DCODE1_RST 64'h02_F9_93_97_02_FA_5C_E3
#define CODESTORE_BYTE7_DCODE1_RST 0x02
#define CODESTORE_BYTE6_DCODE1_RST 0xF9
#define CODESTORE_BYTE5_DCODE1_RST 0x93
#define CODESTORE_BYTE4_DCODE1_RST 0x97
#define CODESTORE_BYTE3_DCODE1_RST 0x02
#define CODESTORE_BYTE2_DCODE1_RST 0xFA
#define CODESTORE_BYTE1_DCODE1_RST 0x5C
#define CODESTORE_BYTE0_DCODE1_RST 0xE3
// -------------------------------
// Preamble - 3 bytes
// -------------------------------
#define PREAMBLE_ADR 0x24
#define PREAMBLE_CODE_MSB_RST 0x33
#define PREAMBLE_CODE_LSB_RST 0x33
#define PREAMBLE_LEN_RST 0x02
// -------------------------------
// Laser Fuses - 8 bytes (2 hidden)
// -------------------------------
#define MFG_ID_ADR 0x25
// -------------------------------
// XTAL Startup Delay
// -------------------------------
#define XTAL_CFG_ADR 0x26
#define XTAL_CFG_RST 0x00
// -------------------------------
// Clock Override
// -------------------------------
#define CLK_OVERRIDE_ADR 0x27
#define CLK_OVERRIDE_RST 0x00
#define RXF 0x02
// -------------------------------
// Clock Enable
// -------------------------------
#define CLK_EN_ADR 0x28
#define CLK_EN_RST 0x00
#define RXF 0x02
// -------------------------------
// Receiver Abort
// -------------------------------
#define RX_ABORT_ADR 0x29
#define RX_ABORT_RST 0x00
#define ABORT_EN 0x20
// -------------------------------
// Auto Calibration Time
// -------------------------------
#define AUTO_CAL_TIME_ADR 0x32
#define AUTO_CAL_TIME_RST 0x0C
#define AUTO_CAL_TIME_MAX 0x3C
// -------------------------------
// Auto Calibration Offset
// -------------------------------
#define AUTO_CAL_OFFSET_ADR 0x35
#define AUTO_CAL_OFFSET_RST 0x00
#define AUTO_CAL_OFFSET_MINUS_4 0x14
#endif // _LpRegs_h_
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