uart0reg.h

基于ARM及CAN总线的源码

/****************************************Copyright (c)**************************************************
**                               广州周立功单片机发展有限公司
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**--------------文件信息--------------------------------------------------------------------------------
**文   件   名: UART0REG.h
**创   建   人: 刘养海
**最后修改日期: 2004年2月25日
**描        述: 定义LPC21xx\LPC22xx中UART0寄存器
**
**--------------历史版本信息----------------------------------------------------------------------------
** 创建人: 刘养海
** 版  本: v1.0
** 日　期: 2004年2月25日
** 描　述: 原始版本
**

**--------------当前版本修订------------------------------------------------------------------------------
** 修改人: 
** 日　期:
** 描　述:
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/
#ifndef	_UART0REG_H_
#define	_UART0REG_H_

/* 通用异步串行口0(UART0)的特殊寄存器地址 */
#define U0RBR_ADR            0xE000C000
#define U0THR_ADR            0xE000C000
#define U0IER_ADR            0xE000C004
#define U0IIR_ADR            0xE000C008
#define U0FCR_ADR            0xE000C008
#define U0LCR_ADR            0xE000C00C
#define U0LSR_ADR            0xE000C014
#define U0SCR_ADR            0xE000C01C
#define U0DLL_ADR            0xE000C000
#define U0DLM_ADR            0xE000C004

//寄存器数据结构定义
//Trans or Rcv
typedef	union	_uartDataF_
{
	UINT32	Word;
	struct	
	{
		UINT32	BR_BIT 		:8;	//缓冲区
		UINT32	RSV_BIT24	:24;/* 	===0;Reserved Bit;*/	
	}Bits;
}uUARTDATAF,*P_uUARTDATAF;

//IER
typedef	union	_uartIE_
{
	UINT32	Word;
	struct	
	{
		UINT32	ERDA_BIT 	:1;	/* 	Enable Rx Data	Available	Interrupt
								*/
		UINT32	ETI_BIT 	:1;	/* 	Enable THRE	Interrupt
								*/
		UINT32	ERSI_BIT 	:1;	/* Enable Rx Line	Status	Interrupt
								*/
		UINT32	RSV_BIT29	:29;/* 	===0;Reserved Bit;*/	
	}Bits;
}uUARTIE,*P_uUARTIE;

//IIR
typedef	union	_uartII_
{
	UINT32	Word;
	struct	
	{
		UINT32	IIR_BIT 	:4;	
		UINT32	RSV_BIT2	:2;	
		UINT32	FFE_BIT 	:2;	
		UINT32	RSV_BIT24	:24;	
	}Bits;
}uUARTII,*P_uUARTII;

//FCR
typedef	union	_uartFC_
{
	UINT32	Word;
	struct	
	{
		UINT32	FE_BIT 		:1;	/* FIFO	Enable
								*/
		UINT32	RFR_BIT 	:1;	/* 	Rx FIFO	Reset
								*/
		UINT32	TFR_BIT 	:1;	/* Tx FIFO	Reset*/
		UINT32	RSV_BIT2	:3;	/* 	===0;Reserved Bit;*/	
		UINT32	RTRG_BIT 	:2;	/* Enable Rx Line	Status	Interrupt*/
		UINT32	RSV_BIT24	:24;/* 	===0;Reserved Bit;*/	
	}Bits;
}uUARTFC,*P_uUARTFC;

//LCR
typedef	union	_uartLC_
{
	UINT32	Word;
	struct	
	{
		UINT32	WLS_BIT 	:2;	/*Word Length	Select
								*/
		UINT32	NSB_BIT 	:1;	/* 	Number	of Stop Bits
								*/
		UINT32	PE_BIT 		:1;	/* Parity	Enable*/
		UINT32	EPS_BIT		:1;	/* Even	Parity	Select*/	
		UINT32	SP_BIT 		:1;	/* Stick	Parity*/
		UINT32	SB_BIT 		:1;	/* Set	Break*/
		UINT32	DLAB_BIT 	:1;	/* DLAB*/
		UINT32	RSV_BIT24	:24;/* 	===0;Reserved Bit;*/	
	}Bits;
}uUARTLC,*P_uUARTLC;

//LSR
typedef	union	_uartLS_
{
	UINT32	Word;
	struct	
	{
		UINT32	DR_BIT 		:1;	
		UINT32	OE_BIT 		:1;	
		UINT32	PE_BIT 		:1;	
		UINT32	FE_BIT		:1;		
		UINT32	BI_BIT		:1;		
		UINT32	THRE_BIT 	:1;	
		UINT32	TEMT_BIT 	:1;	
		UINT32	RFE_BIT 	:1;	
		UINT32	RSV_BIT24	:24;/* 	===0;Reserved Bit;*/	
	}Bits;
}uUARTLS,*P_uUARTLS;


#endif
/*********************************************************************************************************
**                            End Of File
********************************************************************************************************/