📄 kbd.rpt
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-- Node name is '|KEYBOARD:39|:43' = '|KEYBOARD:39|SHIFTIN4'
-- Equation name is '_LC6_C28', type is buried
_LC6_C28 = DFFE( _EQ050, _LC7_C42, VCC, VCC, VCC);
_EQ050 = !_LC5_C45 & _LC6_C28
# !_LC1_C41 & _LC1_C52 & _LC5_C45
# _LC1_C41 & _LC6_C28;
-- Node name is '|KEYBOARD:39|:42' = '|KEYBOARD:39|SHIFTIN5'
-- Equation name is '_LC1_C52', type is buried
_LC1_C52 = DFFE( _EQ051, _LC7_C42, VCC, VCC, VCC);
_EQ051 = _LC1_C52 & !_LC5_C45
# !_LC1_C41 & _LC5_C45 & _LC5_C52
# _LC1_C41 & _LC1_C52;
-- Node name is '|KEYBOARD:39|:41' = '|KEYBOARD:39|SHIFTIN6'
-- Equation name is '_LC5_C52', type is buried
_LC5_C52 = DFFE( _EQ052, _LC7_C42, VCC, VCC, VCC);
_EQ052 = !_LC5_C45 & _LC5_C52
# !_LC1_C41 & _LC5_C45 & _LC7_C52
# _LC1_C41 & _LC5_C52;
-- Node name is '|KEYBOARD:39|:40' = '|KEYBOARD:39|SHIFTIN7'
-- Equation name is '_LC7_C52', type is buried
_LC7_C52 = DFFE( _EQ053, _LC7_C42, VCC, VCC, VCC);
_EQ053 = !_LC5_C45 & _LC7_C52
# !_LC1_C41 & _LC4_C52 & _LC5_C45
# _LC1_C41 & _LC7_C52;
-- Node name is '|KEYBOARD:39|:39' = '|KEYBOARD:39|SHIFTIN8'
-- Equation name is '_LC4_C52', type is buried
_LC4_C52 = DFFE( _EQ054, _LC7_C42, VCC, VCC, VCC);
_EQ054 = _LC4_C52 & !_LC5_C45
# _LC1_C41 & _LC4_C52
# KBD_DATA & !_LC1_C41 & _LC5_C45;
-- Node name is '|KEYBOARD:39|:6'
-- Equation name is '_LC6_C52', type is buried
_LC6_C52 = DFFE( _EQ055, _LC7_C42, VCC, VCC, VCC);
_EQ055 = !_LC1_C41 & !_LC5_C45 & _LC7_C52
# _LC5_C45 & _LC6_C52
# _LC1_C41 & _LC6_C52;
-- Node name is '|KEYBOARD:39|:8'
-- Equation name is '_LC8_C52', type is buried
_LC8_C52 = DFFE( _EQ056, _LC7_C42, VCC, VCC, VCC);
_EQ056 = !_LC1_C41 & !_LC5_C45 & _LC5_C52
# _LC5_C45 & _LC8_C52
# _LC1_C41 & _LC8_C52;
-- Node name is '|KEYBOARD:39|:10'
-- Equation name is '_LC3_C52', type is buried
_LC3_C52 = DFFE( _EQ057, _LC7_C42, VCC, VCC, VCC);
_EQ057 = !_LC1_C41 & _LC1_C52 & !_LC5_C45
# _LC3_C52 & _LC5_C45
# _LC1_C41 & _LC3_C52;
-- Node name is '|KEYBOARD:39|:12'
-- Equation name is '_LC3_C28', type is buried
_LC3_C28 = DFFE( _EQ058, _LC7_C42, VCC, VCC, VCC);
_EQ058 = !_LC1_C41 & !_LC5_C45 & _LC6_C28
# _LC3_C28 & _LC5_C45
# _LC1_C41 & _LC3_C28;
-- Node name is '|KEYBOARD:39|:14'
-- Equation name is '_LC4_C28', type is buried
_LC4_C28 = DFFE( _EQ059, _LC7_C42, VCC, VCC, VCC);
_EQ059 = !_LC1_C41 & !_LC5_C45 & _LC8_C28
# _LC4_C28 & _LC5_C45
# _LC1_C41 & _LC4_C28;
-- Node name is '|KEYBOARD:39|:16'
-- Equation name is '_LC5_C28', type is buried
_LC5_C28 = DFFE( _EQ060, _LC7_C42, VCC, VCC, VCC);
_EQ060 = !_LC1_C41 & !_LC5_C45 & _LC7_C28
# _LC5_C28 & _LC5_C45
# _LC1_C41 & _LC5_C28;
-- Node name is '|KEYBOARD:39|:18'
-- Equation name is '_LC2_C52', type is buried
_LC2_C52 = DFFE( _EQ061, _LC7_C42, VCC, VCC, VCC);
_EQ061 = _LC1_C28 & !_LC1_C41 & !_LC5_C45
# _LC2_C52 & _LC5_C45
# _LC1_C41 & _LC2_C52;
-- Node name is '|KEYBOARD:39|:20'
-- Equation name is '_LC8_C36', type is buried
_LC8_C36 = DFFE( _EQ062, _LC7_C42, VCC, VCC, VCC);
_EQ062 = !_LC1_C41 & _LC2_C28 & !_LC5_C45
# _LC5_C45 & _LC8_C36
# _LC1_C41 & _LC8_C36;
-- Node name is '|KEYBOARD:39|~216~1'
-- Equation name is '_LC4_C31', type is buried
-- synthesized logic cell
_LC4_C31 = LCELL( _EQ063);
_EQ063 = _LC1_C31 & _LC1_C42 & _LC5_C31 & _LC6_C31;
-- Node name is '|KEYBOARD:39|~216~2'
-- Equation name is '_LC5_C42', type is buried
-- synthesized logic cell
_LC5_C42 = LCELL( _EQ064);
_EQ064 = _LC2_C42 & _LC3_C31 & _LC3_C42 & _LC4_C31;
-- Node name is '|KEYBOARD:39|~233~1'
-- Equation name is '_LC2_C31', type is buried
-- synthesized logic cell
_LC2_C31 = LCELL( _EQ065);
_EQ065 = _LC1_C42
# _LC1_C31
# _LC5_C31
# _LC6_C31;
-- Node name is '|KEYBOARD:39|~233~2'
-- Equation name is '_LC6_C42', type is buried
-- synthesized logic cell
_LC6_C42 = LCELL( _EQ066);
_EQ066 = _LC2_C31
# _LC3_C42
# _LC2_C42
# _LC3_C31;
-- Node name is '|KEYBOARD:39|:357'
-- Equation name is '_LC5_C45', type is buried
_LC5_C45 = LCELL( _EQ067);
_EQ067 = !_LC3_C45
# !_LC2_C36 & !_LC6_C45 & !_LC8_C45;
-- Node name is '|KEYBOARD:39|:825'
-- Equation name is '_LC2_C45', type is buried
_LC2_C45 = LCELL( _EQ068);
_EQ068 = !_LC1_C45 & _LC3_C45 & _LC5_C36
# _LC3_C45 & _LC5_C36 & !_LC8_C45
# _LC1_C45 & !_LC3_C45 & _LC5_C36 & _LC8_C45;
-- Node name is '|KEYBOARD:39|:831'
-- Equation name is '_LC7_C45', type is buried
_LC7_C45 = LCELL( _EQ069);
_EQ069 = !_LC2_C36 & _LC5_C36 & _LC8_C45
# _LC5_C36 & !_LC6_C45 & _LC8_C45
# _LC2_C36 & _LC5_C36 & _LC6_C45 & !_LC8_C45;
-- Node name is '|KEYBOARD:39|:837'
-- Equation name is '_LC4_C45', type is buried
_LC4_C45 = LCELL( _EQ070);
_EQ070 = _LC2_C36 & _LC5_C36 & !_LC6_C45
# !_LC2_C36 & _LC5_C36 & _LC6_C45;
-- Node name is '|KEYBOARD:39|~1003~1'
-- Equation name is '_LC1_C41', type is buried
-- synthesized logic cell
!_LC1_C41 = _LC1_C41~NOT;
_LC1_C41~NOT = LCELL( _LC1_C36);
-- Node name is '|KEYBOARD:39|:1065'
-- Equation name is '_LC5_C36', type is buried
_LC5_C36 = LCELL( _EQ071);
_EQ071 = _LC1_C36 & _LC5_C45;
Project Information c:\book_cd\booksoft\chap10\kbd.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 41,393K
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