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📄 kbd.rpt

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💻 RPT
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Total input I/O cell registers required:         0
Total output pins required:                     16
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                     80
Total flipflops required:                       31
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                        17/3744   (  0%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  EA  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  Total(LC/EC)
 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   0   0   0   0   3   0   0   0   8   0   0   0   0   0   0     19/0  
 B:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 C:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   6   0   8   0   7   8   0   0   0   0   1   7   0   0   8   0   0   0   0   0   0   8     61/0  
 D:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 E:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 F:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 G:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 H:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 I:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  

Total:   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   6   0   8   0  15   8   0   0   0   0   1  10   0   0   8   8   0   0   0   0   0   8     80/0  



Device-Specific Information:                c:\book_cd\booksoft\chap10\kbd.rpt
kbd

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  91      -     -    -    --      INPUT  G             0    0    0    0  Clock_25Mhz
  30      -     -    E    --      INPUT                0    0    0    1  KBD_CLK
  31      -     -    E    --      INPUT                0    0    0    5  KBD_DATA


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                c:\book_cd\booksoft\chap10\kbd.rpt
kbd

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  17      -     -    B    --     OUTPUT                0    1    0    0  LSD_SEG_A
  18      -     -    B    --     OUTPUT                0    1    0    0  LSD_SEG_B
  19      -     -    C    --     OUTPUT                0    1    0    0  LSD_SEG_C
  20      -     -    C    --     OUTPUT                0    1    0    0  LSD_SEG_D
  25      -     -    D    --     OUTPUT                0    0    0    0  LSD_SEG_DP
  21      -     -    C    --     OUTPUT                0    1    0    0  LSD_SEG_E
  23      -     -    C    --     OUTPUT                0    1    0    0  LSD_SEG_F
  24      -     -    C    --     OUTPUT                0    1    0    0  LSD_SEG_G
   6      -     -    A    --     OUTPUT                0    1    0    0  MSD_SEG_A
   7      -     -    A    --     OUTPUT                0    1    0    0  MSD_SEG_B
   8      -     -    A    --     OUTPUT                0    1    0    0  MSD_SEG_C
   9      -     -    A    --     OUTPUT                0    1    0    0  MSD_SEG_D
  14      -     -    B    --     OUTPUT                0    0    0    0  MSD_SEG_DP
  11      -     -    A    --     OUTPUT                0    1    0    0  MSD_SEG_E
  12      -     -    B    --     OUTPUT                0    1    0    0  MSD_SEG_F
  13      -     -    B    --     OUTPUT                0    1    0    0  MSD_SEG_G


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                c:\book_cd\booksoft\chap10\kbd.rpt
kbd

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      3     -    A    42        OR2    s           0    2    0    1  |DEC_7SEG:33|~444~1
   -      2     -    A    46       AND2                0    4    0    1  |DEC_7SEG:33|:456
   -      1     -    A    46       AND2                0    4    0    1  |DEC_7SEG:33|:492
   -      4     -    A    35       AND2                0    4    0    3  |DEC_7SEG:33|:528
   -      2     -    A    35        OR2        !       0    4    0    3  |DEC_7SEG:33|:540
   -      1     -    A    42        OR2        !       0    4    1    0  |DEC_7SEG:33|:543
   -      2     -    A    42        OR2        !       0    4    1    0  |DEC_7SEG:33|:591
   -      7     -    A    35        OR2        !       0    4    0    1  |DEC_7SEG:33|:638
   -      5     -    A    35       AND2        !       0    3    1    0  |DEC_7SEG:33|:639
   -      4     -    A    46        OR2    s           0    4    0    1  |DEC_7SEG:33|~687~1
   -      5     -    A    46        OR2    s           0    3    0    1  |DEC_7SEG:33|~687~2
   -      7     -    A    46        OR2    s           0    4    0    1  |DEC_7SEG:33|~687~3
   -      6     -    A    46        OR2        !       0    4    1    0  |DEC_7SEG:33|:687
   -      6     -    A    35        OR2        !       0    4    0    1  |DEC_7SEG:33|:729
   -      8     -    A    35        OR2        !       0    3    1    0  |DEC_7SEG:33|:735
   -      3     -    A    46        OR2    s           0    4    0    1  |DEC_7SEG:33|~771~1
   -      1     -    A    35        OR2        !       0    4    1    0  |DEC_7SEG:33|:783
   -      8     -    A    46        OR2    s           0    3    0    1  |DEC_7SEG:33|~825~1
   -      3     -    A    35        OR2        !       0    4    1    0  |DEC_7SEG:33|:833
   -      2     -    C    35        OR2    s           0    2    0    1  |DEC_7SEG:36|~444~1
   -      2     -    C    33       AND2                0    4    0    1  |DEC_7SEG:36|:456
   -      1     -    C    33       AND2                0    4    0    1  |DEC_7SEG:36|:492
   -      4     -    C    36       AND2                0    4    0    3  |DEC_7SEG:36|:528
   -      3     -    C    36        OR2        !       0    4    0    3  |DEC_7SEG:36|:540
   -      7     -    C    35        OR2        !       0    4    1    0  |DEC_7SEG:36|:543
   -      8     -    C    35        OR2        !       0    4    1    0  |DEC_7SEG:36|:591
   -      4     -    C    35        OR2        !       0    4    0    1  |DEC_7SEG:36|:638
   -      1     -    C    35       AND2        !       0    3    1    0  |DEC_7SEG:36|:639
   -      5     -    C    33        OR2    s           0    4    0    1  |DEC_7SEG:36|~687~1
   -      6     -    C    33        OR2    s           0    3    0    1  |DEC_7SEG:36|~687~2
   -      7     -    C    33        OR2    s           0    4    0    1  |DEC_7SEG:36|~687~3
   -      3     -    C    33        OR2        !       0    4    1    0  |DEC_7SEG:36|:687
   -      3     -    C    35        OR2        !       0    4    0    1  |DEC_7SEG:36|:729
   -      5     -    C    35        OR2        !       0    3    1    0  |DEC_7SEG:36|:735
   -      4     -    C    33        OR2    s           0    4    0    1  |DEC_7SEG:36|~771~1
   -      6     -    C    36        OR2        !       0    4    1    0  |DEC_7SEG:36|:783
   -      8     -    C    33        OR2    s           0    3    0    1  |DEC_7SEG:36|~825~1
   -      7     -    C    36        OR2        !       0    4    1    0  |DEC_7SEG:36|:833
   -      1     -    C    45       AND2                0    2    0    1  |KEYBOARD:39|LPM_ADD_SUB:440|addcore:adder|:55
   -      6     -    C    52       DFFE                0    4    0   14  |KEYBOARD:39|:6
   -      8     -    C    52       DFFE                0    4    0   14  |KEYBOARD:39|:8
   -      3     -    C    52       DFFE                0    4    0   14  |KEYBOARD:39|:10
   -      3     -    C    28       DFFE                0    4    0   12  |KEYBOARD:39|:12
   -      4     -    C    28       DFFE                0    4    0   14  |KEYBOARD:39|:14
   -      5     -    C    28       DFFE                0    4    0   14  |KEYBOARD:39|:16
   -      2     -    C    52       DFFE                0    4    0   14  |KEYBOARD:39|:18
   -      8     -    C    36       DFFE                0    4    0   12  |KEYBOARD:39|:20
   -      1     -    C    31       DFFE   +            1    0    0    3  |KEYBOARD:39|filter7 (|KEYBOARD:39|:25)
   -      5     -    C    31       DFFE   +            0    1    0    3  |KEYBOARD:39|filter6 (|KEYBOARD:39|:26)
   -      6     -    C    31       DFFE   +            0    1    0    3  |KEYBOARD:39|filter5 (|KEYBOARD:39|:27)
   -      3     -    C    31       DFFE   +            0    1    0    3  |KEYBOARD:39|filter4 (|KEYBOARD:39|:28)
   -      2     -    C    42       DFFE   +            0    1    0    3  |KEYBOARD:39|filter3 (|KEYBOARD:39|:29)
   -      3     -    C    42       DFFE   +            0    1    0    3  |KEYBOARD:39|filter2 (|KEYBOARD:39|:30)
   -      4     -    C    42       DFFE   +            0    1    0    2  |KEYBOARD:39|filter1 (|KEYBOARD:39|:31)
   -      1     -    C    42       DFFE   +            0    1    0    2  |KEYBOARD:39|filter0 (|KEYBOARD:39|:32)
   -      7     -    C    42       DFFE   +            0    3    0   22  |KEYBOARD:39|keyboard_clk_filtered (|KEYBOARD:39|:33)
   -      3     -    C    45       DFFE                1    3    0    2  |KEYBOARD:39|INCNT3 (|KEYBOARD:39|:34)
   -      8     -    C    45       DFFE                1    3    0    3  |KEYBOARD:39|INCNT2 (|KEYBOARD:39|:35)
   -      6     -    C    45       DFFE                1    3    0    4  |KEYBOARD:39|INCNT1 (|KEYBOARD:39|:36)
   -      2     -    C    36       DFFE                0    3    0    4  |KEYBOARD:39|INCNT0 (|KEYBOARD:39|:37)
   -      1     -    C    36       DFFE                1    2    0    6  |KEYBOARD:39|READ_CHAR (|KEYBOARD:39|:38)
   -      4     -    C    52       DFFE                1    3    0    1  |KEYBOARD:39|SHIFTIN8 (|KEYBOARD:39|:39)
   -      7     -    C    52       DFFE                0    4    0    2  |KEYBOARD:39|SHIFTIN7 (|KEYBOARD:39|:40)
   -      5     -    C    52       DFFE                0    4    0    2  |KEYBOARD:39|SHIFTIN6 (|KEYBOARD:39|:41)
   -      1     -    C    52       DFFE                0    4    0    2  |KEYBOARD:39|SHIFTIN5 (|KEYBOARD:39|:42)
   -      6     -    C    28       DFFE                0    4    0    2  |KEYBOARD:39|SHIFTIN4 (|KEYBOARD:39|:43)
   -      8     -    C    28       DFFE                0    4    0    2  |KEYBOARD:39|SHIFTIN3 (|KEYBOARD:39|:44)
   -      7     -    C    28       DFFE                0    4    0    2  |KEYBOARD:39|SHIFTIN2 (|KEYBOARD:39|:45)
   -      1     -    C    28       DFFE                0    4    0    2  |KEYBOARD:39|SHIFTIN1 (|KEYBOARD:39|:46)
   -      2     -    C    28       DFFE                0    4    0    1  |KEYBOARD:39|SHIFTIN0 (|KEYBOARD:39|:47)
   -      4     -    C    31       AND2    s           0    4    0    1  |KEYBOARD:39|~216~1
   -      5     -    C    42       AND2    s           0    4    0    1  |KEYBOARD:39|~216~2
   -      2     -    C    31        OR2    s           0    4    0    1  |KEYBOARD:39|~233~1
   -      6     -    C    42        OR2    s           0    4    0    1  |KEYBOARD:39|~233~2
   -      5     -    C    45        OR2                0    4    0   20  |KEYBOARD:39|:357
   -      2     -    C    45        OR2                0    4    0    1  |KEYBOARD:39|:825
   -      7     -    C    45        OR2                0    4    0    1  |KEYBOARD:39|:831
   -      4     -    C    45        OR2                0    3    0    1  |KEYBOARD:39|:837
   -      1     -    C    41       AND2    s   !       0    1    0   17  |KEYBOARD:39|~1003~1
   -      5     -    C    36       AND2                0    2    0    3  |KEYBOARD:39|:1065


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                c:\book_cd\booksoft\chap10\kbd.rpt
kbd

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       1/208(  0%)     0/104(  0%)    11/104( 10%)    0/16(  0%)      5/16( 31%)     0/16(  0%)
B:       0/208(  0%)     0/104(  0%)     4/104(  3%)    0/16(  0%)      5/16( 31%)     0/16(  0%)
C:       2/208(  0%)     0/104(  0%)    27/104( 25%)    0/16(  0%)      5/16( 31%)     0/16(  0%)
D:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
E:       2/208(  0%)     0/104(  0%)     0/104(  0%)    2/16( 12%)      0/16(  0%)     0/16(  0%)
F:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
G:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
H:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
I:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
25:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
26:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
27:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
28:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
29:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

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