prev_cmp_keyboard.tan.qmsg

有關鍵盤

{ "Info" "ITDB_TSU_RESULT" "filter\[7\] keyboard_clk clock_50Mhz 3.788 ns register " "Info: tsu for register \"filter\[7\]\" (data pin = \"keyboard_clk\", clock pin = \"clock_50Mhz\") is 3.788 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.514 ns + Longest pin register " "Info: + Longest pin to register delay is 6.514 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.872 ns) 0.872 ns keyboard_clk 1 PIN PIN_D26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.872 ns) = 0.872 ns; Loc. = PIN_D26; Fanout = 1; PIN Node = 'keyboard_clk'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyboard_clk } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.409 ns) + CELL(0.149 ns) 6.430 ns filter\[7\]~feeder 2 COMB LCCOMB_X64_Y19_N26 1 " "Info: 2: + IC(5.409 ns) + CELL(0.149 ns) = 6.430 ns; Loc. = LCCOMB_X64_Y19_N26; Fanout = 1; COMB Node = 'filter\[7\]~feeder'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.558 ns" { keyboard_clk filter[7]~feeder } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.514 ns filter\[7\] 3 REG LCFF_X64_Y19_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.514 ns; Loc. = LCFF_X64_Y19_N27; Fanout = 2; REG Node = 'filter\[7\]'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { filter[7]~feeder filter[7] } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.105 ns ( 16.96 % ) " "Info: Total cell delay = 1.105 ns ( 16.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.409 ns ( 83.04 % ) " "Info: Total interconnect delay = 5.409 ns ( 83.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.514 ns" { keyboard_clk filter[7]~feeder filter[7] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "6.514 ns" { keyboard_clk {} keyboard_clk~combout {} filter[7]~feeder {} filter[7] {} } { 0.000ns 0.000ns 5.409ns 0.000ns } { 0.000ns 0.872ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50Mhz destination 2.690 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_50Mhz\" to destination register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock_50Mhz 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_50Mhz } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock_50Mhz~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clock_50Mhz~clkctrl'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clock_50Mhz clock_50Mhz~clkctrl } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns filter\[7\] 3 REG LCFF_X64_Y19_N27 2 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N27; Fanout = 2; REG Node = 'filter\[7\]'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clock_50Mhz~clkctrl filter[7] } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clock_50Mhz clock_50Mhz~clkctrl filter[7] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clock_50Mhz {} clock_50Mhz~combout {} clock_50Mhz~clkctrl {} filter[7] {} } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.514 ns" { keyboard_clk filter[7]~feeder filter[7] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "6.514 ns" { keyboard_clk {} keyboard_clk~combout {} filter[7]~feeder {} filter[7] {} } { 0.000ns 0.000ns 5.409ns 0.000ns } { 0.000ns 0.872ns 0.149ns 0.084ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clock_50Mhz clock_50Mhz~clkctrl filter[7] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clock_50Mhz {} clock_50Mhz~combout {} clock_50Mhz~clkctrl {} filter[7] {} } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock_50Mhz scan_ready scan_ready~reg0 10.997 ns register " "Info: tco from clock \"clock_50Mhz\" to destination pin \"scan_ready\" through register \"scan_ready~reg0\" is 10.997 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50Mhz source 7.265 ns + Longest register " "Info: + Longest clock path from clock \"clock_50Mhz\" to source register is 7.265 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock_50Mhz 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_50Mhz } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.954 ns) + CELL(0.787 ns) 3.740 ns keyboard_clk_filtered 2 REG LCFF_X64_Y19_N1 5 " "Info: 2: + IC(1.954 ns) + CELL(0.787 ns) = 3.740 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.741 ns" { clock_50Mhz keyboard_clk_filtered } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.787 ns) 6.032 ns ready_set 3 REG LCFF_X62_Y3_N13 2 " "Info: 3: + IC(1.505 ns) + CELL(0.787 ns) = 6.032 ns; Loc. = LCFF_X62_Y3_N13; Fanout = 2; REG Node = 'ready_set'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.292 ns" { keyboard_clk_filtered ready_set } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.537 ns) 7.265 ns scan_ready~reg0 4 REG LCFF_X60_Y3_N17 1 " "Info: 4: + IC(0.696 ns) + CELL(0.537 ns) = 7.265 ns; Loc. = LCFF_X60_Y3_N17; Fanout = 1; REG Node = 'scan_ready~reg0'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.233 ns" { ready_set scan_ready~reg0 } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 24 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.110 ns ( 42.81 % ) " "Info: Total cell delay = 3.110 ns ( 42.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.155 ns ( 57.19 % ) " "Info: Total interconnect delay = 4.155 ns ( 57.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "7.265 ns" { clock_50Mhz keyboard_clk_filtered ready_set scan_ready~reg0 } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "7.265 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} ready_set {} scan_ready~reg0 {} } { 0.000ns 0.000ns 1.954ns 1.505ns 0.696ns } { 0.000ns 0.999ns 0.787ns 0.787ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 24 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.482 ns + Longest register pin " "Info: + Longest register to pin delay is 3.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan_ready~reg0 1 REG LCFF_X60_Y3_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X60_Y3_N17; Fanout = 1; REG Node = 'scan_ready~reg0'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_ready~reg0 } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 24 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(2.808 ns) 3.482 ns scan_ready 2 PIN PIN_AE22 0 " "Info: 2: + IC(0.674 ns) + CELL(2.808 ns) = 3.482 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'scan_ready'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.482 ns" { scan_ready~reg0 scan_ready } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.808 ns ( 80.64 % ) " "Info: Total cell delay = 2.808 ns ( 80.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.674 ns ( 19.36 % ) " "Info: Total interconnect delay = 0.674 ns ( 19.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.482 ns" { scan_ready~reg0 scan_ready } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.482 ns" { scan_ready~reg0 {} scan_ready {} } { 0.000ns 0.674ns } { 0.000ns 2.808ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "7.265 ns" { clock_50Mhz keyboard_clk_filtered ready_set scan_ready~reg0 } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "7.265 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} ready_set {} scan_ready~reg0 {} } { 0.000ns 0.000ns 1.954ns 1.505ns 0.696ns } { 0.000ns 0.999ns 0.787ns 0.787ns 0.537ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.482 ns" { scan_ready~reg0 scan_ready } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.482 ns" { scan_ready~reg0 {} scan_ready {} } { 0.000ns 0.674ns } { 0.000ns 2.808ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "INCNT\[2\] reset clock_50Mhz 2.727 ns register " "Info: th for register \"INCNT\[2\]\" (data pin = \"reset\", clock pin = \"clock_50Mhz\") is 2.727 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50Mhz destination 5.944 ns + Longest register " "Info: + Longest clock path from clock \"clock_50Mhz\" to destination register is 5.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock_50Mhz 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_50Mhz } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.954 ns) + CELL(0.787 ns) 3.740 ns keyboard_clk_filtered 2 REG LCFF_X64_Y19_N1 5 " "Info: 2: + IC(1.954 ns) + CELL(0.787 ns) = 3.740 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.741 ns" { clock_50Mhz keyboard_clk_filtered } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.639 ns) + CELL(0.000 ns) 4.379 ns keyboard_clk_filtered~clkctrl 3 COMB CLKCTRL_G7 22 " "Info: 3: + IC(0.639 ns) + CELL(0.000 ns) = 4.379 ns; Loc. = CLKCTRL_G7; Fanout = 22; COMB Node = 'keyboard_clk_filtered~clkctrl'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { keyboard_clk_filtered keyboard_clk_filtered~clkctrl } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 5.944 ns INCNT\[2\] 4 REG LCFF_X62_Y3_N25 3 " "Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 5.944 ns; Loc. = LCFF_X62_Y3_N25; Fanout = 3; REG Node = 'INCNT\[2\]'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { keyboard_clk_filtered~clkctrl INCNT[2] } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 39.08 % ) " "Info: Total cell delay = 2.323 ns ( 39.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.621 ns ( 60.92 % ) " "Info: Total interconnect delay = 3.621 ns ( 60.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.944 ns" { clock_50Mhz keyboard_clk_filtered keyboard_clk_filtered~clkctrl INCNT[2] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.944 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} keyboard_clk_filtered~clkctrl {} INCNT[2] {} } { 0.000ns 0.000ns 1.954ns 0.639ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.483 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns reset 1 PIN PIN_N26 10 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 10; PIN Node = 'reset'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.250 ns) + CELL(0.150 ns) 3.399 ns INCNT~224 2 COMB LCCOMB_X62_Y3_N24 1 " "Info: 2: + IC(2.250 ns) + CELL(0.150 ns) = 3.399 ns; Loc. = LCCOMB_X62_Y3_N24; Fanout = 1; COMB Node = 'INCNT~224'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { reset INCNT~224 } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.483 ns INCNT\[2\] 3 REG LCFF_X62_Y3_N25 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.483 ns; Loc. = LCFF_X62_Y3_N25; Fanout = 3; REG Node = 'INCNT\[2\]'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { INCNT~224 INCNT[2] } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.233 ns ( 35.40 % ) " "Info: Total cell delay = 1.233 ns ( 35.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.250 ns ( 64.60 % ) " "Info: Total interconnect delay = 2.250 ns ( 64.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.483 ns" { reset INCNT~224 INCNT[2] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.483 ns" { reset {} reset~combout {} INCNT~224 {} INCNT[2] {} } { 0.000ns 0.000ns 2.250ns 0.000ns } { 0.000ns 0.999ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.944 ns" { clock_50Mhz keyboard_clk_filtered keyboard_clk_filtered~clkctrl INCNT[2] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.944 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} keyboard_clk_filtered~clkctrl {} INCNT[2] {} } { 0.000ns 0.000ns 1.954ns 0.639ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.483 ns" { reset INCNT~224 INCNT[2] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.483 ns" { reset {} reset~combout {} INCNT~224 {} INCNT[2] {} } { 0.000ns 0.000ns 2.250ns 0.000ns } { 0.000ns 0.999ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "127 " "Info: Peak virtual memory: 127 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 06 13:32:22 2008 " "Info: Processing ended: Thu Nov 06 13:32:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}