keyboard.tan.qmsg

有關鍵盤

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ready_set " "Info: Detected ripple clock \"ready_set\" as buffer" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 17 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ready_set" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keyboard_clk_filtered " "Info: Detected ripple clock \"keyboard_clk_filtered\" as buffer" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "keyboard_clk_filtered" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_50Mhz register INCNT\[1\] register scan_code\[0\]~reg0 375.8 MHz 2.661 ns Internal " "Info: Clock \"clock_50Mhz\" has Internal fmax of 375.8 MHz between source register \"INCNT\[1\]\" and destination register \"scan_code\[0\]~reg0\" (period= 2.661 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.447 ns + Longest register register " "Info: + Longest register to register delay is 2.447 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns INCNT\[1\] 1 REG LCFF_X62_Y3_N27 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X62_Y3_N27; Fanout = 3; REG Node = 'INCNT\[1\]'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { INCNT[1] } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.438 ns) 0.958 ns LessThan0~44 2 COMB LCCOMB_X62_Y3_N0 8 " "Info: 2: + IC(0.520 ns) + CELL(0.438 ns) = 0.958 ns; Loc. = LCCOMB_X62_Y3_N0; Fanout = 8; COMB Node = 'LessThan0~44'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.958 ns" { INCNT[1] LessThan0~44 } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/80sp1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.261 ns) + CELL(0.150 ns) 1.369 ns scan_code\[0\]~159 3 COMB LCCOMB_X62_Y3_N10 8 " "Info: 3: + IC(0.261 ns) + CELL(0.150 ns) = 1.369 ns; Loc. = LCCOMB_X62_Y3_N10; Fanout = 8; COMB Node = 'scan_code\[0\]~159'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.411 ns" { LessThan0~44 scan_code[0]~159 } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.418 ns) + CELL(0.660 ns) 2.447 ns scan_code\[0\]~reg0 4 REG LCFF_X61_Y3_N17 1 " "Info: 4: + IC(0.418 ns) + CELL(0.660 ns) = 2.447 ns; Loc. = LCFF_X61_Y3_N17; Fanout = 1; REG Node = 'scan_code\[0\]~reg0'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.078 ns" { scan_code[0]~159 scan_code[0]~reg0 } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.248 ns ( 51.00 % ) " "Info: Total cell delay = 1.248 ns ( 51.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.199 ns ( 49.00 % ) " "Info: Total interconnect delay = 1.199 ns ( 49.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.447 ns" { INCNT[1] LessThan0~44 scan_code[0]~159 scan_code[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.447 ns" { INCNT[1] {} LessThan0~44 {} scan_code[0]~159 {} scan_code[0]~reg0 {} } { 0.000ns 0.520ns 0.261ns 0.418ns } { 0.000ns 0.438ns 0.150ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50Mhz destination 5.944 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_50Mhz\" to destination register is 5.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock_50Mhz 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_50Mhz } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.954 ns) + CELL(0.787 ns) 3.740 ns keyboard_clk_filtered 2 REG LCFF_X64_Y19_N1 5 " "Info: 2: + IC(1.954 ns) + CELL(0.787 ns) = 3.740 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.741 ns" { clock_50Mhz keyboard_clk_filtered } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.639 ns) + CELL(0.000 ns) 4.379 ns keyboard_clk_filtered~clkctrl 3 COMB CLKCTRL_G7 22 " "Info: 3: + IC(0.639 ns) + CELL(0.000 ns) = 4.379 ns; Loc. = CLKCTRL_G7; Fanout = 22; COMB Node = 'keyboard_clk_filtered~clkctrl'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { keyboard_clk_filtered keyboard_clk_filtered~clkctrl } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 5.944 ns scan_code\[0\]~reg0 4 REG LCFF_X61_Y3_N17 1 " "Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 5.944 ns; Loc. = LCFF_X61_Y3_N17; Fanout = 1; REG Node = 'scan_code\[0\]~reg0'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { keyboard_clk_filtered~clkctrl scan_code[0]~reg0 } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 39.08 % ) " "Info: Total cell delay = 2.323 ns ( 39.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.621 ns ( 60.92 % ) " "Info: Total interconnect delay = 3.621 ns ( 60.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.944 ns" { clock_50Mhz keyboard_clk_filtered keyboard_clk_filtered~clkctrl scan_code[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.944 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} keyboard_clk_filtered~clkctrl {} scan_code[0]~reg0 {} } { 0.000ns 0.000ns 1.954ns 0.639ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50Mhz source 5.944 ns - Longest register " "Info: - Longest clock path from clock \"clock_50Mhz\" to source register is 5.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock_50Mhz 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_50Mhz } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.954 ns) + CELL(0.787 ns) 3.740 ns keyboard_clk_filtered 2 REG LCFF_X64_Y19_N1 5 " "Info: 2: + IC(1.954 ns) + CELL(0.787 ns) = 3.740 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.741 ns" { clock_50Mhz keyboard_clk_filtered } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.639 ns) + CELL(0.000 ns) 4.379 ns keyboard_clk_filtered~clkctrl 3 COMB CLKCTRL_G7 22 " "Info: 3: + IC(0.639 ns) + CELL(0.000 ns) = 4.379 ns; Loc. = CLKCTRL_G7; Fanout = 22; COMB Node = 'keyboard_clk_filtered~clkctrl'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { keyboard_clk_filtered keyboard_clk_filtered~clkctrl } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 5.944 ns INCNT\[1\] 4 REG LCFF_X62_Y3_N27 3 " "Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 5.944 ns; Loc. = LCFF_X62_Y3_N27; Fanout = 3; REG Node = 'INCNT\[1\]'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { keyboard_clk_filtered~clkctrl INCNT[1] } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 39.08 % ) " "Info: Total cell delay = 2.323 ns ( 39.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.621 ns ( 60.92 % ) " "Info: Total interconnect delay = 3.621 ns ( 60.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.944 ns" { clock_50Mhz keyboard_clk_filtered keyboard_clk_filtered~clkctrl INCNT[1] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.944 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} keyboard_clk_filtered~clkctrl {} INCNT[1] {} } { 0.000ns 0.000ns 1.954ns 0.639ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.944 ns" { clock_50Mhz keyboard_clk_filtered keyboard_clk_filtered~clkctrl scan_code[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.944 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} keyboard_clk_filtered~clkctrl {} scan_code[0]~reg0 {} } { 0.000ns 0.000ns 1.954ns 0.639ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.944 ns" { clock_50Mhz keyboard_clk_filtered keyboard_clk_filtered~clkctrl INCNT[1] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.944 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} keyboard_clk_filtered~clkctrl {} INCNT[1] {} } { 0.000ns 0.000ns 1.954ns 0.639ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 72 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.447 ns" { INCNT[1] LessThan0~44 scan_code[0]~159 scan_code[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.447 ns" { INCNT[1] {} LessThan0~44 {} scan_code[0]~159 {} scan_code[0]~reg0 {} } { 0.000ns 0.520ns 0.261ns 0.418ns } { 0.000ns 0.438ns 0.150ns 0.660ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.944 ns" { clock_50Mhz keyboard_clk_filtered keyboard_clk_filtered~clkctrl scan_code[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.944 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} keyboard_clk_filtered~clkctrl {} scan_code[0]~reg0 {} } { 0.000ns 0.000ns 1.954ns 0.639ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "5.944 ns" { clock_50Mhz keyboard_clk_filtered keyboard_clk_filtered~clkctrl INCNT[1] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "5.944 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} keyboard_clk_filtered~clkctrl {} INCNT[1] {} } { 0.000ns 0.000ns 1.954ns 0.639ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clock_50Mhz 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clock_50Mhz\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "filter\[0\] keyboard_clk_filtered clock_50Mhz 16 ps " "Info: Found hold time violation between source  pin or register \"filter\[0\]\" and destination pin or register \"keyboard_clk_filtered\" for clock \"clock_50Mhz\" (Hold time is 16 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.800 ns + Largest " "Info: + Largest clock skew is 0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50Mhz destination 3.490 ns + Longest register " "Info: + Longest clock path from clock \"clock_50Mhz\" to destination register is 3.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock_50Mhz 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_50Mhz } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.954 ns) + CELL(0.537 ns) 3.490 ns keyboard_clk_filtered 2 REG LCFF_X64_Y19_N1 5 " "Info: 2: + IC(1.954 ns) + CELL(0.537 ns) = 3.490 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.491 ns" { clock_50Mhz keyboard_clk_filtered } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 44.01 % ) " "Info: Total cell delay = 1.536 ns ( 44.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.954 ns ( 55.99 % ) " "Info: Total interconnect delay = 1.954 ns ( 55.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.490 ns" { clock_50Mhz keyboard_clk_filtered } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.490 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} } { 0.000ns 0.000ns 1.954ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_50Mhz source 2.690 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_50Mhz\" to source register is 2.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock_50Mhz 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_50Mhz } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock_50Mhz~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clock_50Mhz~clkctrl'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clock_50Mhz clock_50Mhz~clkctrl } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.690 ns filter\[0\] 3 REG LCFF_X64_Y19_N13 1 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N13; Fanout = 1; REG Node = 'filter\[0\]'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clock_50Mhz~clkctrl filter[0] } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.10 % ) " "Info: Total cell delay = 1.536 ns ( 57.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 42.90 % ) " "Info: Total interconnect delay = 1.154 ns ( 42.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clock_50Mhz clock_50Mhz~clkctrl filter[0] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clock_50Mhz {} clock_50Mhz~combout {} clock_50Mhz~clkctrl {} filter[0] {} } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.490 ns" { clock_50Mhz keyboard_clk_filtered } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.490 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} } { 0.000ns 0.000ns 1.954ns } { 0.000ns 0.999ns 0.537ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clock_50Mhz clock_50Mhz~clkctrl filter[0] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clock_50Mhz {} clock_50Mhz~combout {} clock_50Mhz~clkctrl {} filter[0] {} } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.800 ns - Shortest register register " "Info: - Shortest register to register delay is 0.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns filter\[0\] 1 REG LCFF_X64_Y19_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y19_N13; Fanout = 1; REG Node = 'filter\[0\]'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { filter[0] } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns keyboard_clk_filtered~107 2 COMB LCCOMB_X64_Y19_N12 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X64_Y19_N12; Fanout = 1; COMB Node = 'keyboard_clk_filtered~107'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.323 ns" { filter[0] keyboard_clk_filtered~107 } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.243 ns) + CELL(0.150 ns) 0.716 ns keyboard_clk_filtered~108 3 COMB LCCOMB_X64_Y19_N0 1 " "Info: 3: + IC(0.243 ns) + CELL(0.150 ns) = 0.716 ns; Loc. = LCCOMB_X64_Y19_N0; Fanout = 1; COMB Node = 'keyboard_clk_filtered~108'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { keyboard_clk_filtered~107 keyboard_clk_filtered~108 } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.800 ns keyboard_clk_filtered 4 REG LCFF_X64_Y19_N1 5 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 0.800 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'" {  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { keyboard_clk_filtered~108 keyboard_clk_filtered } "NODE_NAME" } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.557 ns ( 69.63 % ) " "Info: Total cell delay = 0.557 ns ( 69.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.243 ns ( 30.38 % ) " "Info: Total interconnect delay = 0.243 ns ( 30.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { filter[0] keyboard_clk_filtered~107 keyboard_clk_filtered~108 keyboard_clk_filtered } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "0.800 ns" { filter[0] {} keyboard_clk_filtered~107 {} keyboard_clk_filtered~108 {} keyboard_clk_filtered {} } { 0.000ns 0.000ns 0.243ns 0.000ns } { 0.000ns 0.323ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.490 ns" { clock_50Mhz keyboard_clk_filtered } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.490 ns" { clock_50Mhz {} clock_50Mhz~combout {} keyboard_clk_filtered {} } { 0.000ns 0.000ns 1.954ns } { 0.000ns 0.999ns 0.537ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.690 ns" { clock_50Mhz clock_50Mhz~clkctrl filter[0] } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "2.690 ns" { clock_50Mhz {} clock_50Mhz~combout {} clock_50Mhz~clkctrl {} filter[0] {} } { 0.000ns 0.000ns 0.118ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { filter[0] keyboard_clk_filtered~107 keyboard_clk_filtered~108 keyboard_clk_filtered } "NODE_NAME" } } { "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "0.800 ns" { filter[0] {} keyboard_clk_filtered~107 {} keyboard_clk_filtered~108 {} keyboard_clk_filtered {} } { 0.000ns 0.000ns 0.243ns 0.000ns } { 0.000ns 0.323ns 0.150ns 0.084ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}