prev_cmp_keyboard.fit.qmsg

有關鍵盤

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 06 13:31:47 2008 " "Info: Processing started: Thu Nov 06 13:31:47 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off keyboard -c keyboard " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off keyboard -c keyboard" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "keyboard EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"keyboard\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 0}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock incremental compilation " "Warning: Feature LogicLock incremental compilation is not available with your current license" {  } {  } 0 0 "Feature %1!s! is not available with your current license" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" {  } { { "d:/program files/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/80sp1/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" {  } { { "d:/program files/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/80sp1/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" {  } { { "d:/program files/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/80sp1/quartus/bin/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock_50Mhz (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clock_50Mhz (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "keyboard_clk_filtered " "Info: Destination node keyboard_clk_filtered" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyboard_clk_filtered } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "d:/program files/altera/80sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/80sp1/quartus/bin/pin_planner.ppl" { clock_50Mhz } } } { "d:/program files/altera/80sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/80sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock_50Mhz" } } } } { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 7 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_50Mhz } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "keyboard_clk_filtered  " "Info: Automatically promoted node keyboard_clk_filtered " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ready_set " "Info: Destination node ready_set" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 17 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ready_set } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "keyboard_clk_filtered~106 " "Info: Destination node keyboard_clk_filtered~106" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyboard_clk_filtered~106 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "keyboard_clk_filtered~107 " "Info: Destination node keyboard_clk_filtered~107" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyboard_clk_filtered~107 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "keyboard_clk_filtered~108 " "Info: Destination node keyboard_clk_filtered~108" {  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyboard_clk_filtered~108 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "KEYBOARD.VHD" "" { Text "D:/work/DCL/keyboard/KEYBOARD.VHD" 18 -1 0 } } { "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyboard_clk_filtered } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 0}