keyboard.tan.rpt

有關鍵盤

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition
    Info: Processing started: Mon Nov 24 12:01:43 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off keyboard -c keyboard --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock_50Mhz" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "ready_set" as buffer
    Info: Detected ripple clock "keyboard_clk_filtered" as buffer
Info: Clock "clock_50Mhz" has Internal fmax of 375.8 MHz between source register "INCNT[1]" and destination register "scan_code[0]~reg0" (period= 2.661 ns)
    Info: + Longest register to register delay is 2.447 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X62_Y3_N27; Fanout = 3; REG Node = 'INCNT[1]'
        Info: 2: + IC(0.520 ns) + CELL(0.438 ns) = 0.958 ns; Loc. = LCCOMB_X62_Y3_N0; Fanout = 8; COMB Node = 'LessThan0~44'
        Info: 3: + IC(0.261 ns) + CELL(0.150 ns) = 1.369 ns; Loc. = LCCOMB_X62_Y3_N10; Fanout = 8; COMB Node = 'scan_code[0]~159'
        Info: 4: + IC(0.418 ns) + CELL(0.660 ns) = 2.447 ns; Loc. = LCFF_X61_Y3_N17; Fanout = 1; REG Node = 'scan_code[0]~reg0'
        Info: Total cell delay = 1.248 ns ( 51.00 % )
        Info: Total interconnect delay = 1.199 ns ( 49.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock_50Mhz" to destination register is 5.944 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'
            Info: 2: + IC(1.954 ns) + CELL(0.787 ns) = 3.740 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'
            Info: 3: + IC(0.639 ns) + CELL(0.000 ns) = 4.379 ns; Loc. = CLKCTRL_G7; Fanout = 22; COMB Node = 'keyboard_clk_filtered~clkctrl'
            Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 5.944 ns; Loc. = LCFF_X61_Y3_N17; Fanout = 1; REG Node = 'scan_code[0]~reg0'
            Info: Total cell delay = 2.323 ns ( 39.08 % )
            Info: Total interconnect delay = 3.621 ns ( 60.92 % )
        Info: - Longest clock path from clock "clock_50Mhz" to source register is 5.944 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'
            Info: 2: + IC(1.954 ns) + CELL(0.787 ns) = 3.740 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'
            Info: 3: + IC(0.639 ns) + CELL(0.000 ns) = 4.379 ns; Loc. = CLKCTRL_G7; Fanout = 22; COMB Node = 'keyboard_clk_filtered~clkctrl'
            Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 5.944 ns; Loc. = LCFF_X62_Y3_N27; Fanout = 3; REG Node = 'INCNT[1]'
            Info: Total cell delay = 2.323 ns ( 39.08 % )
            Info: Total interconnect delay = 3.621 ns ( 60.92 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "clock_50Mhz" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "filter[0]" and destination pin or register "keyboard_clk_filtered" for clock "clock_50Mhz" (Hold time is 16 ps)
    Info: + Largest clock skew is 0.800 ns
        Info: + Longest clock path from clock "clock_50Mhz" to destination register is 3.490 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'
            Info: 2: + IC(1.954 ns) + CELL(0.537 ns) = 3.490 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'
            Info: Total cell delay = 1.536 ns ( 44.01 % )
            Info: Total interconnect delay = 1.954 ns ( 55.99 % )
        Info: - Shortest clock path from clock "clock_50Mhz" to source register is 2.690 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clock_50Mhz~clkctrl'
            Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N13; Fanout = 1; REG Node = 'filter[0]'
            Info: Total cell delay = 1.536 ns ( 57.10 % )
            Info: Total interconnect delay = 1.154 ns ( 42.90 % )
    Info: - Micro clock to output delay of source is 0.250 ns
    Info: - Shortest register to register delay is 0.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y19_N13; Fanout = 1; REG Node = 'filter[0]'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X64_Y19_N12; Fanout = 1; COMB Node = 'keyboard_clk_filtered~107'
        Info: 3: + IC(0.243 ns) + CELL(0.150 ns) = 0.716 ns; Loc. = LCCOMB_X64_Y19_N0; Fanout = 1; COMB Node = 'keyboard_clk_filtered~108'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 0.800 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'
        Info: Total cell delay = 0.557 ns ( 69.63 % )
        Info: Total interconnect delay = 0.243 ns ( 30.38 % )
    Info: + Micro hold delay of destination is 0.266 ns
Info: tsu for register "filter[7]" (data pin = "keyboard_clk", clock pin = "clock_50Mhz") is 3.788 ns
    Info: + Longest pin to register delay is 6.514 ns
        Info: 1: + IC(0.000 ns) + CELL(0.872 ns) = 0.872 ns; Loc. = PIN_D26; Fanout = 1; PIN Node = 'keyboard_clk'
        Info: 2: + IC(5.409 ns) + CELL(0.149 ns) = 6.430 ns; Loc. = LCCOMB_X64_Y19_N26; Fanout = 1; COMB Node = 'filter[7]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.514 ns; Loc. = LCFF_X64_Y19_N27; Fanout = 2; REG Node = 'filter[7]'
        Info: Total cell delay = 1.105 ns ( 16.96 % )
        Info: Total interconnect delay = 5.409 ns ( 83.04 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clock_50Mhz" to destination register is 2.690 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clock_50Mhz~clkctrl'
        Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X64_Y19_N27; Fanout = 2; REG Node = 'filter[7]'
        Info: Total cell delay = 1.536 ns ( 57.10 % )
        Info: Total interconnect delay = 1.154 ns ( 42.90 % )
Info: tco from clock "clock_50Mhz" to destination pin "scan_ready" through register "scan_ready~reg0" is 10.997 ns
    Info: + Longest clock path from clock "clock_50Mhz" to source register is 7.265 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'
        Info: 2: + IC(1.954 ns) + CELL(0.787 ns) = 3.740 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'
        Info: 3: + IC(1.505 ns) + CELL(0.787 ns) = 6.032 ns; Loc. = LCFF_X62_Y3_N13; Fanout = 2; REG Node = 'ready_set'
        Info: 4: + IC(0.696 ns) + CELL(0.537 ns) = 7.265 ns; Loc. = LCFF_X60_Y3_N17; Fanout = 1; REG Node = 'scan_ready~reg0'
        Info: Total cell delay = 3.110 ns ( 42.81 % )
        Info: Total interconnect delay = 4.155 ns ( 57.19 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.482 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X60_Y3_N17; Fanout = 1; REG Node = 'scan_ready~reg0'
        Info: 2: + IC(0.674 ns) + CELL(2.808 ns) = 3.482 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'scan_ready'
        Info: Total cell delay = 2.808 ns ( 80.64 % )
        Info: Total interconnect delay = 0.674 ns ( 19.36 % )
Info: th for register "INCNT[2]" (data pin = "reset", clock pin = "clock_50Mhz") is 2.727 ns
    Info: + Longest clock path from clock "clock_50Mhz" to destination register is 5.944 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clock_50Mhz'
        Info: 2: + IC(1.954 ns) + CELL(0.787 ns) = 3.740 ns; Loc. = LCFF_X64_Y19_N1; Fanout = 5; REG Node = 'keyboard_clk_filtered'
        Info: 3: + IC(0.639 ns) + CELL(0.000 ns) = 4.379 ns; Loc. = CLKCTRL_G7; Fanout = 22; COMB Node = 'keyboard_clk_filtered~clkctrl'
        Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 5.944 ns; Loc. = LCFF_X62_Y3_N25; Fanout = 3; REG Node = 'INCNT[2]'
        Info: Total cell delay = 2.323 ns ( 39.08 % )
        Info: Total interconnect delay = 3.621 ns ( 60.92 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 3.483 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 10; PIN Node = 'reset'
        Info: 2: + IC(2.250 ns) + CELL(0.150 ns) = 3.399 ns; Loc. = LCCOMB_X62_Y3_N24; Fanout = 1; COMB Node = 'INCNT~224'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.483 ns; Loc. = LCFF_X62_Y3_N25; Fanout = 3; REG Node = 'INCNT[2]'
        Info: Total cell delay = 1.233 ns ( 35.40 % )
        Info: Total interconnect delay = 2.250 ns ( 64.60 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 127 megabytes
    Info: Processing ended: Mon Nov 24 12:01:44 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01