📄 rtxconf.a51
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;
?RTX_TIMER2_TYPE EQU ?RTX_T2_80515_FAMILY
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0
DB 02H, 00H, 00H ; INT_1, Timer 0
DB 04H, 00H, 00H ; INT_2
DB 08H, 00H, 00H ; INT_3, Timer 1
DB 10H, 00H, 00H ; INT_4
DB 20H, 00H, 00H ; INT_5, Timer 2
DB 00H, 00H, 00H ; not used
DB 00H, 00H, 00H ; not used
DB 00H, 01H, 00H ; INT_8
DB 00H, 02H, 00H ; INT_9
DB 00H, 04H, 00H ; INT_10
DB 00H, 08H, 00H ; INT_11
DB 00H, 10H, 00H ; INT_12
DB 00H, 20H, 00H ; INT_13
; Define the greatest supported interrupt number
;
?RTX_MAX_INT_NBR EQU 13
; Enter Idle Mode Macro
; Used whenever entering idle state. Peripherals stay active.
; Leaved after interrupt.
;
PCON DATA 87H
ENTER_IDLE MACRO
ORL PCON, #01H ; Set idle mode
ORL PCON, #20H
ENDM
; Define the register addresses to set the MSB of the page address.
;
?RTX_PAGE_OUT_REG DATA 0A0H ; write directly to Port 2
ELSEIF (?RTX_CPU_TYPE = 4)
; Define the number and addresses of the interrupt enable registers.
; Set the not used registers to the same address as ?RTX_IE
;
INT_EN_MASK_NUMBER EQU 3
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0B8H
?RTX_IEN2 DATA 09AH
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
;
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 8
INT_ENTRY 9
INT_ENTRY 10
INT_ENTRY 11
INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 16
INT_ENTRY 19
ELSEIF (?RTX_SYSTEM_TIMER = 1)
; Do NOT include the Timer 1 Vector (INT-3)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 8
INT_ENTRY 9
INT_ENTRY 10
INT_ENTRY 11
INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 16
INT_ENTRY 19
ELSEIF (?RTX_SYSTEM_TIMER = 2)
; Do NOT include the Timer 2 Vector (INT-5)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 8
INT_ENTRY 9
INT_ENTRY 10
INT_ENTRY 11
INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 16
INT_ENTRY 19
ENDIF
; Select the Timer 2 configuration.
;
?RTX_TIMER2_TYPE EQU ?RTX_T2_80515_FAMILY
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0
DB 02H, 00H, 00H ; INT_1, Timer 0
DB 04H, 00H, 00H ; INT_2
DB 08H, 00H, 00H ; INT_3, Timer 1
DB 10H, 00H, 00H ; INT_4
DB 20H, 00H, 00H ; INT_5, Timer 2
DB 00H, 00H, 00H ; not used
DB 00H, 00H, 00H ; not used
DB 00H, 01H, 00H ; INT_8
DB 00H, 02H, 00H ; INT_9
DB 00H, 04H, 00H ; INT_10
DB 00H, 08H, 00H ; INT_11
DB 00H, 10H, 00H ; INT_12
DB 00H, 20H, 00H ; INT_13
DB 00H, 00H, 00H ; not used
DB 00H, 00H, 00H ; not used
DB 00H, 00H, 01H ; INT_16
DB 00H, 00H, 00H ; not used
DB 00H, 00H, 00H ; not used
DB 00H, 00H, 08H ; INT_19
; Define the greatest supported interrupt number
;
?RTX_MAX_INT_NBR EQU 19
; Enter Idle Mode Macro
; Used whenever entering idle state. Peripherals stay active.
; Leaved after interrupt.
;
PCON DATA 87H
ENTER_IDLE MACRO
ORL PCON, #01H ; Set idle mode
ORL PCON, #20H
ENDM
; Define the register addresses to set the MSB of the page address.
;
?RTX_PAGE_OUT_REG DATA 0A0H ; write directly to Port 2
ELSEIF (?RTX_CPU_TYPE = 5)
; Define the number and addresses of the interrupt enable registers.
; Set the not used registers to the same address as ?RTX_IE
;
INT_EN_MASK_NUMBER EQU 1
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0A8H ; not used
?RTX_IEN2 DATA 0A8H ; not used
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
;
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 6
ELSEIF (?RTX_SYSTEM_TIMER = 1)
; Do NOT include the Timer 1 Vector (INT-3)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 6
ELSEIF (?RTX_SYSTEM_TIMER = 2)
; Do NOT include the Timer 2 Vector (INT-5)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 6
ENDIF
; Select the Timer 2 configuration.
;
?RTX_TIMER2_TYPE EQU ?RTX_T2_STANDARD
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0
DB 02H, 00H, 00H ; INT_1, Timer 0
DB 04H, 00H, 00H ; INT_2
DB 08H, 00H, 00H ; INT_3, Timer 1
DB 10H, 00H, 00H ; INT_4
DB 20H, 00H, 00H ; INT_5, Timer 2
DB 40H, 00H, 00H ; INT_6
; Define the greatest supported interrupt number
;
?RTX_MAX_INT_NBR EQU 6
; Enter Idle Mode Macro
; Used whenever entering idle state. Peripherals stay active.
; Leaved after interrupt.
;
PCON DATA 87H
ENTER_IDLE MACRO
ORL PCON, #01H ; Set idle mode
ENDM
; Define the register addresses to set the MSB of the page address.
;
?RTX_PAGE_OUT_REG DATA 0A0H ; write directly to Port 2
ELSEIF (?RTX_CPU_TYPE = 6) OR (?RTX_CPU_TYPE = 7)
; Define the number and addresses of the interrupt enable registers.
; Set the not used registers to the same address as ?RTX_IE
;
INT_EN_MASK_NUMBER EQU 2
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0E8H
?RTX_IEN2 DATA 0A8H ; not used
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
;
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 6
INT_ENTRY 7
INT_ENTRY 8
INT_ENTRY 9
INT_ENTRY 10
INT_ENTRY 11
INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 14
ELSEIF (?RTX_SYSTEM_TIMER = 1)
; Do NOT include the Timer 1 Vector (INT-3)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 6
INT_ENTRY 7
INT_ENTRY 8
INT_ENTRY 9
INT_ENTRY 10
INT_ENTRY 11
INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 14
ENDIF
; Select the Timer 2 configuration.
;
?RTX_TIMER2_TYPE EQU ?RTX_T2_NOT_SUPPORTED ; Timer 2 not supported as System Timer
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0
DB 02H, 00H, 00H ; INT_1, Timer 0
DB 04H, 00H, 00H ; INT_2
DB 08H, 00H, 00H ; INT_3, Timer 1
DB 10H, 00H, 00H ; INT_4
DB 20H, 00H, 00H ; INT_5
DB 00H, 01H, 00H ; INT_6
DB 00H, 02H, 00H ; INT_7
DB 00H, 04H, 00H ; INT_8
DB 00H, 08H, 00H ; INT_9
DB 40H, 00H, 00H ; INT_10
DB 00H, 10H, 00H ; INT_11
DB 00H, 20H, 00H ; INT_12
DB 00H, 40H, 00H ; INT_13
DB 00H, 80H, 00H ; INT_14
; Define the greatest supported interrupt number
;
?RTX_MAX_INT_NBR EQU 14
; Enter Idle Mode Macro
; Used whenever entering idle state. Peripherals stay active.
; Leaved after interrupt.
;
PCON DATA 87H
ENTER_IDLE MACRO
ORL PCON, #01H ; Set idle mode
ENDM
; Define the register addresses to set the MSB of the page address.
;
?RTX_PAGE_OUT_REG DATA 0A0H ; write directly to Port 2
ELSEIF (?RTX_CPU_TYPE = 8)
; Define the number and addresses of the interrupt enable registers.
; Set the not used registers to the same address as ?RTX_IE
;
INT_EN_MASK_NUMBER EQU 2
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0C8H
?RTX_IEN2 DATA 0A8H ; not used
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
;
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 6
INT_ENTRY 7
INT_ENTRY 8
INT_ENTRY 9
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