📄 rtxconf.lst
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4582 ?RTX?INT_MASK?RTXCONF SEGMENT DATA
---- 4583 RSEG ?RTX?INT_MASK?RTXCONF
4584 ; variables for first mask
0000 4585 ?RTX_NM_IE: DS 1
0001 4586 ?RTX_D_IE: DS 1
0002 4587 ?RTX_ND_IE: DS 1
4588 ; variables for second mask (not used)
0003 4589 ?RTX_NM_IE1: DS 0
0003 4590 ?RTX_D_IE1: DS 0
0003 4591 ?RTX_ND_IE1: DS 0
4592 ; variables for third mask (not used)
0003 4593 ?RTX_NM_IE2: DS 0
0003 4594 ?RTX_D_IE2: DS 0
0003 4595 ?RTX_ND_IE2: DS 0
4596
4597 ; RTX-51 calls this routine in the initialisation phase
4598 ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF SEGMENT CODE
---- 4599 RSEG ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF
0000 4600 ?RTX_INIT_INT_REG_FLAGS:
0000 C200 F 4601 CLR ?RTX_ENA_INT_REG1
0002 C200 F 4602 CLR ?RTX_ENA_INT_REG2
0004 22 4603 RET
ENDIF
4651
4652
4653 ;------------------------------------------------------------------
4654 ; Define the System-Timer specific values
4655 ; This values are normally for all 8051 family-members identical.
4656 ;
ELSEIF (?RTX_SYSTEM_TIMER = 1)
008B 4678 ?RTX_TLOW DATA 8BH
008D 4679 ?RTX_THIGH DATA 8DH
0088 4680 ?RTX_TCON DATA 88H
0089 4681 ?RTX_TMOD DATA 89H
008F 4682 ?RTX_TFLAG BIT 8FH
008E 4683 ?RTX_TCONTROL BIT 8EH
4684 ; TCON init-masks
4685 ; The clock will be initialized with: ANL TCON, #RTX_TCON_AND_MASK
4686 ; ORL TCON, #RTX_TCON_OR_MASK
4687 ; --> not used for this timer
00FF 4688 ?RTX_TCON_AND_MASK EQU 0FFH
0000 4689 ?RTX_TCON_OR_MASK EQU 000H
4690 ; TMOD init-masks
4691 ; The clock will be initialized with: ANL TMOD, #RTX_TMOD_AND_MASK
4692 ; ORL TMOD, #RTX_TMOD_OR_MASK
000F 4693 ?RTX_TMOD_AND_MASK EQU 0FH
0010 4694 ?RTX_TMOD_OR_MASK EQU 10H
4695 ; Interrupt Vector Entry
0003 4696 ?RTX_CLK_INT_NBR EQU 3
ENDIF
4772
4773 ;------------------------------------------------------------------
4774 ; System-Timer Interrupt Vector Entry
4775 ;
---- 4776 CSEG AT(?RTX_INTBASE+3+(8*?RTX_CLK_INT_NBR))
ENDIF
001B 020000 F 4780 LJMP ?RTX_SYSCLK_INTHNDLR
4781
4782 ;------------------------------------------------------------------
4783 ; Definitions for Code-Bank-Switching Support
4784 ;
4785 IF (?RTX_BANKSWITCHING = 0)
4786 ; Dummy definitions when no Bank-Switching is used
4787 ; (just to satisfy the Linker)
4788 ;
0000 4789 ?B_CURRENTBANK EQU 0H
0000 4790 ?RTX_SWITCHBANK EQU 0H
0000 4791 ?RTX_SAVE_INT_BANK EQU 0H
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 13
ENDIF
4836
4837
4838 ;------------------------------------------------------------------
4839 ; Context-space in each Fast-Task stack in internal RAM
4840 ;
4841 IF (?RTX_BANKSWITCHING = 0)
0003 4842 ?RTX_INTREGSIZE EQU 3 ; SP/reentrant SP (P2:?C_PBP)
ENDIF
4846
4847 ;------------------------------------------------------------------
4848 ;
4849 ; RTX Idle Function
4850 ;
4851 ; RTX-51 jumps to this code when entering the idle loop
4852
4853 ?RTX?RTX_IDLE_FUNC?RTXCONF SEGMENT CODE
---- 4854 RSEG ?RTX?RTX_IDLE_FUNC?RTXCONF
0000 4855 ?RTX_IDLE_FUNC:
ENDIF
0000 80FE 4860 JMP ?RTX_IDLE_FUNC
4861
4862 ;------------------------------------------------------------------
4863 ; Define the Fast-Task stack and context space
4864 ;
4865 ?RTX?FTASKDATA?U SEGMENT IDATA
---- 4866 RSEG ?RTX?FTASKDATA?U
0000 4867 DS ?RTX_INTSTKSIZE
4868
4869
4870 ;------------------------------------------------------------------
4871 ; Define the mailbox FIFOs
4872 ; ========================
4873 ; NOTE: this segment must be page-aligned; do not change !
4874
4875 ?RTX?RTX_MBX_PAGE SEGMENT XDATA PAGE
---- 4876 RSEG ?RTX?RTX_MBX_PAGE
4877
4878 IF (?RTX_MAILBOX_SUPPORT = 1)
0000 4879 ?RTX_MBX_PAGE: DS 8*32
ENDIF
0100 4883 ?RTX_MBX_PAGE_END: DS 0
4884
4885
4886 ;------------------------------------------------------------------
4887 ; Define the semaphore FIFOs
4888 ; ==========================
4889 ; NOTE: this segment must be page-aligned; do not change !
4890
4891 ?RTX?RTX_SEM_PAGE SEGMENT XDATA PAGE
---- 4892 RSEG ?RTX?RTX_SEM_PAGE
4893
4894 IF (?RTX_SEMAPHORE_SUPPORT = 1)
0000 4895 ?RTX_SEM_PAGE: DS 8*16
ENDIF
0080 4899 ?RTX_SEM_PAGE_END: DS 0
4900
4901
4902 ;*----------------------------------------------------------------------*
4903 ;* END OF MODULE
4904 ;*----------------------------------------------------------------------*
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 14
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES
?B_CURRENTBANK. . . . . . . . . . . N NUMB 0000H A
?RTX?CONFIGURATION. . . . . . . . . N NUMB -----
?RTX?FTASKDATA?U. . . . . . . . . . I SEG 0018H REL=UNIT
?RTX?INT_MASK?RTXCONF . . . . . . . D SEG 0003H REL=UNIT
?RTX?RTX_IDLE_FUNC?RTXCONF. . . . . C SEG 0002H REL=UNIT
?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF C SEG 0005H REL=UNIT
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF . C SEG 0012H REL=UNIT
?RTX?RTX_MBX_PAGE . . . . . . . . . X SEG 0100H REL=PAGE
?RTX?RTX_SEM_PAGE . . . . . . . . . X SEG 0080H REL=PAGE
?RTX_BANKSWITCHING. . . . . . . . . N NUMB 0000H A
?RTX_CLK_INT_NBR. . . . . . . . . . N NUMB 0003H A
?RTX_CPU_TYPE . . . . . . . . . . . N NUMB 0002H A
?RTX_D_IE . . . . . . . . . . . . . D ADDR 0001H R SEG=?RTX?INT_MASK?RTXCONF
?RTX_D_IE1. . . . . . . . . . . . . D ADDR 0003H R SEG=?RTX?INT_MASK?RTXCONF
?RTX_D_IE2. . . . . . . . . . . . . D ADDR 0003H R SEG=?RTX?INT_MASK?RTXCONF
?RTX_ENA_INT_REG1 . . . . . . . . . B ADDR ----- EXT
?RTX_ENA_INT_REG2 . . . . . . . . . B ADDR ----- EXT
?RTX_EXTRENTSIZE. . . . . . . . . . N NUMB 0032H A
?RTX_EXTSTKSIZE . . . . . . . . . . N NUMB 0020H A
?RTX_IDLE_FUNC. . . . . . . . . . . C ADDR 0000H R SEG=?RTX?RTX_IDLE_FUNC?RTXCONF
?RTX_IE . . . . . . . . . . . . . . D ADDR 00A8H A
?RTX_IEN1 . . . . . . . . . . . . . D ADDR 00A8H A
?RTX_IEN1_INIT. . . . . . . . . . . N NUMB 0000H A
?RTX_IEN2 . . . . . . . . . . . . . D ADDR 00A8H A
?RTX_IEN2_INIT. . . . . . . . . . . N NUMB 0000H A
?RTX_IE_INIT. . . . . . . . . . . . N NUMB 0000H A
?RTX_INIT_INT_REG_FLAGS . . . . . . C ADDR 0000H R SEG=?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF
?RTX_INT0_TID . . . . . . . . . . . X ADDR ----- EXT
?RTX_INT1_TID . . . . . . . . . . . X ADDR ----- EXT
?RTX_INT2_TID . . . . . . . . . . . X ADDR ----- EXT
?RTX_INT4_TID . . . . . . . . . . . X ADDR ----- EXT
?RTX_INT5_TID . . . . . . . . . . . X ADDR ----- EXT
?RTX_INTBASE. . . . . . . . . . . . N NUMB 0000H A
?RTX_INTREGSIZE . . . . . . . . . . N NUMB 0003H A
?RTX_INTSTKSIZE . . . . . . . . . . N NUMB 0018H A
?RTX_INT_HANDLER. . . . . . . . . . C ADDR ----- EXT
?RTX_INT_TO_BIT_TABLE_BASE. . . . . C ADDR 0000H R SEG=?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_MAILBOX_SUPPORT. . . . . . . . N NUMB 0001H A
?RTX_MAX_INT_NBR. . . . . . . . . . N NUMB 0005H A
?RTX_MBX_PAGE . . . . . . . . . . . X ADDR 0000H R SEG=?RTX?RTX_MBX_PAGE
?RTX_MBX_PAGE_END . . . . . . . . . X ADDR 0100H R SEG=?RTX?RTX_MBX_PAGE
?RTX_ND_IE. . . . . . . . . . . . . D ADDR 0002H R SEG=?RTX?INT_MASK?RTXCONF
?RTX_ND_IE1 . . . . . . . . . . . . D ADDR 0003H R SEG=?RTX?INT_MASK?RTXCONF
?RTX_ND_IE2 . . . . . . . . . . . . D ADDR 0003H R SEG=?RTX?INT_MASK?RTXCONF
?RTX_NM_IE. . . . . . . . . . . . . D ADDR 0000H R SEG=?RTX?INT_MASK?RTXCONF
?RTX_NM_IE1 . . . . . . . . . . . . D ADDR 0003H R SEG=?RTX?INT_MASK?RTXCONF
?RTX_NM_IE2 . . . . . . . . . . . . D ADDR 0003H R SEG=?RTX?INT_MASK?RTXCONF⌨️ 快捷键说明
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