📄 rtxconf.lst
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542 ;* --------------------------------------------------------------- *
543 ;* *
544 ;************************************************************************
545
546 NAME ?RTX?CONFIGURATION ; Do NOT alter the modulename !
547
548 ;*----------------------------------------------------------------------*
549 ;* IMPORTS
550 ;*----------------------------------------------------------------------*
551
552 EXTRN BIT (?RTX_ENA_INT_REG1, ?RTX_ENA_INT_REG2) ; from RTXDATA
553 EXTRN CODE (?RTX_SYSCLK_INTHNDLR) ; from RTXCLK
554 EXTRN CODE (?RTX_INT_HANDLER) ; from RTXINT
555 EXTRN DATA (?RTX_TMP1) ; from RTXDATA
556
ENDIF
562
563 ;*----------------------------------------------------------------------*
564 ;* EXPORTS
565 ;*----------------------------------------------------------------------*
566
567 ; System constants
568 PUBLIC ?RTX_EXTRENTSIZE, ?RTX_EXTSTKSIZE, ?RTX_INTSTKSIZE
569 PUBLIC ?RTX_TIMESHARING, ?RTX_BANKSWITCHING, ?RTX_INTREGSIZE
570 PUBLIC ?RTX_MAILBOX_SUPPORT, ?RTX_SEMAPHORE_SUPPORT
571
572 ; Initial Interrupt mask values
573 PUBLIC ?RTX_IE_INIT, ?RTX_IEN1_INIT, ?RTX_IEN2_INIT
574
575 ; Enable the interrupt enable registers for the selected processor
576 PUBLIC ?RTX_INIT_INT_REG_FLAGS
577
578 ; Interrupt number to enable-mask table
579 PUBLIC ?RTX_INT_TO_BIT_TABLE_BASE
580
581 ; Greatest interrupt number
582 PUBLIC ?RTX_MAX_INT_NBR
583
584 ; Processor specific interrupt enable masks
585 PUBLIC ?RTX_IE, ?RTX_IEN1, ?RTX_IEN2
586
587 ; Interrupt mask variables
588 PUBLIC ?RTX_NM_IE, ?RTX_D_IE, ?RTX_ND_IE
589 PUBLIC ?RTX_NM_IE1, ?RTX_D_IE1, ?RTX_ND_IE1
590 PUBLIC ?RTX_NM_IE2, ?RTX_D_IE2, ?RTX_ND_IE2
591
592 ; System Timer constants
593 PUBLIC ?RTX_CLK_INT_NBR ; EQUATE
594 PUBLIC ?RTX_TLOW, ?RTX_THIGH, ?RTX_TMOD ; DATA
595 PUBLIC ?RTX_TCON ; DATA
596 PUBLIC ?RTX_TFLAG, ?RTX_TCONTROL ; BIT
597 PUBLIC ?RTX_TMOD_AND_MASK, ?RTX_TMOD_OR_MASK ; EQUATES
598 PUBLIC ?RTX_TCON_AND_MASK, ?RTX_TCON_OR_MASK ; EQUATES
599
600 ; Bank-Switching Support
601 PUBLIC ?RTX_SWITCHBANK ; CODE
602 PUBLIC ?RTX_SAVE_INT_BANK ; DATA
603 IF (?RTX_BANKSWITCHING = 0)
604 PUBLIC ?B_CURRENTBANK ; Dummy DATA-Definition
605 ENDIF
606
607 ; Idle function
608 PUBLIC ?RTX_IDLE_FUNC
609
610 ; Page addressing register
611 PUBLIC ?RTX_PAGE_OUT_REG
612
613 ; Mailbox and semaphore FIFO space
614 PUBLIC ?RTX_MBX_PAGE
615 PUBLIC ?RTX_MBX_PAGE_END
616 PUBLIC ?RTX_SEM_PAGE
617 PUBLIC ?RTX_SEM_PAGE_END
618
619
620 ;*----------------------------------------------------------------------*
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 10
621 ;* TIMER 2 CONFIGURATION TYPES
622 ;*----------------------------------------------------------------------*
623
0000 624 ?RTX_T2_NONE EQU 0 ; CPU without timer 2
0000 625 ?RTX_T2_NOT_SUPPORTED EQU 0 ; Timer 2 not supported as system timer
0001 626 ?RTX_T2_STANDARD EQU 1 ; Standard 8052
0002 627 ?RTX_T2_NO_T2MOD EQU 2 ; Timer 2 without T2MOD register
0003 628 ?RTX_T2_80515_FAMILY EQU 3 ; Timer 2 for the Infineon 80515 family
629
630 ;*----------------------------------------------------------------------*
631 ;* MACROS
632 ;*----------------------------------------------------------------------*
633
634 ; This MACRO generates an RTX-51 interrupt entry point using the base
635 ; address ?RTX_INTBASE.
636
637 INT_ENTRY MACRO NO
638 EXTRN XDATA (?RTX_INT&NO&_TID)
639 PUBLIC INT&NO&_VECTOR
640 CSEG AT(?RTX_INTBASE+3+(&NO&*8))
641 INT&NO&_VECTOR: MOV ?RTX_TMP1, A ; Save A
642 MOV A, #LOW(?RTX_INT&NO&_TID); Set up ptr to int. TID
643 LJMP ?RTX_INT_HANDLER ; Jump to general ISR
644 ENDM
645
646
647 ;*----------------------------------------------------------------------*
648 ;* PROCESSOR SPECIFIC DATA DEFINITIONS
649 ;*----------------------------------------------------------------------*
650
ELSEIF (?RTX_CPU_TYPE = 2)
719
720 ; Define the number and addresses of the interrupt enable registers.
721 ; Set the not used registers to the same address as ?RTX_IE
722 ;
0001 723 INT_EN_MASK_NUMBER EQU 1
00A8 724 ?RTX_IE DATA 0A8H
00A8 725 ?RTX_IEN1 DATA 0A8H ; not used
00A8 726 ?RTX_IEN2 DATA 0A8H ; not used
727
728 ; Generate the interrupt entry points supported by the peripherals
729 ; of the selected CPU type.
730 ;
ELSEIF (?RTX_SYSTEM_TIMER = 1)
739 ; Do NOT include the Timer 1 Vector (INT-3)
740 INT_ENTRY 0
747 INT_ENTRY 1
754 INT_ENTRY 2
761 INT_ENTRY 4
768 INT_ENTRY 5
ENDIF
783
784 ; Select the Timer 2 configuration.
785 ;
0001 786 ?RTX_TIMER2_TYPE EQU ?RTX_T2_STANDARD
787
788 ; The following table attaches the interrupt numbers (0..31) to the
789 ; corresponding bits in the interrupt enable masks of the specific
790 ; processor.
791 ; All three interrupt enable register contents must be defined
792 ; for every interrupt number (even when the specific processor contains
793 ; only one interrupt mask).
794 ; Syntax: DB IE-content, IE1-content, IE2-content
795 ;
796 ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
---- 797 RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
798
0000 799 ?RTX_INT_TO_BIT_TABLE_BASE:
0000 010000 800 DB 01H, 00H, 00H ; INT_0
0003 020000 801 DB 02H, 00H, 00H ; INT_1, Timer 0
0006 040000 802 DB 04H, 00H, 00H ; INT_2
0009 080000 803 DB 08H, 00H, 00H ; INT_3, Timer 1
000C 100000 804 DB 10H, 00H, 00H ; INT_4
000F 200000 805 DB 20H, 00H, 00H ; INT_5, Timer 2
806
807 ; Define the greatest supported interrupt number
808 ;
0005 809 ?RTX_MAX_INT_NBR EQU 5
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 11
810
811 ; Enter Idle Mode Macro
812 ; Used whenever entering idle state. Peripherals stay active.
813 ; Leaved after interrupt.
814 ;
0087 815 PCON DATA 87H
816 ENTER_IDLE MACRO
817 ORL PCON, #01H ; Set idle mode
818 ENDM
819
820 ; Define the register addresses to set the MSB of the page address.
821 ;
00A0 822 ?RTX_PAGE_OUT_REG DATA 0A0H ; write directly to Port 2
823
824
ENDIF
4568
4569
4570
4571 $eject
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 12
4572 ;*----------------------------------------------------------------------*
4573 ;* DEFINITIONS COMMON FOR ALL PROCESSORS
4574 ;*----------------------------------------------------------------------*
4575
4576 ;------------------------------------------------------------------
4577 ; Define the internal interrupt mask variables. The variables are
4578 ; used for the Interrupt-Handling.
4579 ; Initialise the enable bits for the Interrupt-Enable-Masks
4580 ;
4581 IF (INT_EN_MASK_NUMBER = 1)
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