📄 rtxconf.lst
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+1 362 ; Winbond W78LE812 35
+1 363 ;
+1 364 ; [*1] Version V7.00: Errors corrected
+1 365 ;
+1 366 ; [*2] Timer 2 not supported as System Timer
+1 367 ;
+1 368 ; [*3] PFI (power fail interrupt): not supported by RTX as task interrupt.
+1 369 ; May be used by C51 interrupt functions only.
+1 370 ;
0002 +1 371 ?RTX_CPU_TYPE EQU 2
+1 372
+1 373
+1 374 ; 2. SYSTEM CLOCK
+1 375 ; ===============
+1 376 ;
+1 377 ; (Baiscally Timer 0, Timer 1 and Timer 2 are supported)
+1 378 ; Set ?RTX_SYSTEM_TIMER to 0 for Timer 0
+1 379 ; Set ?RTX_SYSTEM_TIMER to 1 for Timer 1
+1 380 ; Set ?RTX_SYSTEM_TIMER to 2 for Timer 2
+1 381 ; NOTE: Timer 2 is not supported for all CPU types. If it is specified
+1 382 ; for a not supported CPU type, then an error message will be
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 6
+1 383 ; generated when assembling RTXCONF.A51.
+1 384 ; (Default-value: Timer 0)
+1 385 ;
0001 +1 386 ?RTX_SYSTEM_TIMER EQU 1
+1 387
+1 388
+1 389
+1 390 ; 3. INITIAL INTERRUPT-ENABLE REGISTER VALUES
+1 391 ; ===========================================
+1 392 ;
+1 393 ; Some 8051 family members have specific bits in their Interrupt-Enable
+1 394 ; Registers, which have other functions than interrupt enable/disable.
+1 395 ; Here you can set the initial values of these special bits.
+1 396 ; (Normally RTX-51 will set all not used bits in the interrupt enable mask
+1 397 ; to 0).
+1 398 ; You MUST NOT set bits dedicated to interrupt enable/disable !
+1 399 ; NOTE: ?RTX_IEN1_INIT is only used for processors with at least 2 interrupt
+1 400 ; masks.
+1 401 ; ?RTX_IEN2_INIT is only used for processors with 3 interrupt masks.
+1 402 ;
0000 +1 403 ?RTX_IE_INIT EQU 00H
0000 +1 404 ?RTX_IEN1_INIT EQU 00H
0000 +1 405 ?RTX_IEN2_INIT EQU 00H
+1 406
+1 407
+1 408 ; 4. FAST TASK STACK- AND ENVIRONMENT SIZE
+1 409 ; ========================================
+1 410 ;
+1 411 ; This constant defines the stack- and environment size reserved per
+1 412 ; defined fast task. These areas are located in IDATA space.
+1 413 ;
+1 414 ; Minimum values (per task):
+1 415 ; - 3 Bytes for internal use
+1 416 ; - 2 Bytes for the task code start address
+1 417 ; Do not set to less than 9 bytes
+1 418 ; Add 3 Bytes when code bank switching is used (?RTX_BANKSWITCHING = 1) !
+1 419 ; (Default value: 12 Bytes)
+1 420 ;
0018 +1 421 ?RTX_INTSTKSIZE EQU 24
+1 422
+1 423
+1 424 ; 5. STANDARD TASK CONTEXT STACK SIZE
+1 425 ; ===================================
+1 426 ;
+1 427 ; This constant defines the maximum size of stack data stored in the
+1 428 ; context area of a standard task. For each defined standard task such an
+1 429 ; area is reserved in XDATA space.
+1 430 ;
+1 431 ; (Default value: 32 Bytes)
+1 432 ;
0020 +1 433 ?RTX_EXTSTKSIZE EQU 32
+1 434
+1 435
+1 436 ; 6. REENTRANT STACK SIZE
+1 437 ; =======================
+1 438 ;
+1 439 ; This constnat defines the maximum size of the reentrant stack. For each
+1 440 ; defined task such an area is reserved in XDATA space.
+1 441 ;
+1 442 ; The greatest possible reentrant-stack size is 256-18-?RTX_EXTSTKSIZE !!
+1 443 ; (Default value: 50 Bytes)
+1 444 ;
0032 +1 445 ?RTX_EXTRENTSIZE EQU 50
+1 446
+1 447
+1 448 ; 7. ROUND ROBIN FLAG
+1 449 ; ===================
+1 450 ;
+1 451 ; 0 --> Do not use round robin scheduling
+1 452 ; 1 --> Use round robin scheduling
+1 453 ; (Default value: 0)
+1 454 ;
0000 +1 455 ?RTX_TIMESHARING EQU 0
+1 456
+1 457
+1 458 ; 8. BANK SWITCHING FLAG
+1 459 ; ======================
+1 460 ;
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 7
+1 461 ; For code bank switching details see BL51 documentation and READ.ME file
+1 462 ; 0 --> code bank switching is disabled
+1 463 ; 1 --> code bank switching is enabled
+1 464 ; (Default value: 0)
+1 465 ;
+1 466 ; !!! IMPORTANT NOTICE !!!
+1 467 ; Set ?B_RTX contained in L51_BANK.A51 (V1.4b up) to one, when using
+1 468 ; code bank switching together with RTX-51
+1 469 ;
0000 +1 470 ?RTX_BANKSWITCHING EQU 0
+1 471
+1 472
+1 473 ; 9. INTERRUPT TABLE BASE ADDRESS
+1 474 ; ===============================
+1 475 ;
+1 476 ; Normally the interrupt table is located at address 0000H. For special
+1 477 ; hardware configurations, like flash eprom systems, there may be a need
+1 478 ; to reroute interrupts to a table at a different address. If an address
+1 479 ; different than 0000H is used, then the user has to supply code to re-
+1 480 ; route each used interrupt vector to an address with the offset declared
+1 481 ; below.
+1 482 ; For standard systems this address has to be 0000H.
+1 483 ;
0000 +1 484 ?RTX_INTBASE EQU 0000H
+1 485
+1 486
+1 487 ; 10. MAILBOX-SUPPORT FLAG
+1 488 ; ========================
+1 489 ;
+1 490 ; This flag determines if memory is allocated for the mailbox FIFOs or not.
+1 491 ; If set to 0, then no wait for a mailbox is possible. Associated calls
+1 492 ; will return a NOT_OK in this case.
+1 493 ; Set ?RTX_MAILBOX_SUPPORT to 0 if mailbox services are not desired.
+1 494 ; Set ?RTX_MAILBOX_SUPPORT to 1 if mailbox services are desired.
+1 495 ; (Default is 1)
+1 496 ;
0001 +1 497 ?RTX_MAILBOX_SUPPORT EQU 1
+1 498
+1 499
+1 500 ; 11. SEMAPHORE-SUPPORT FLAG
+1 501 ; ==========================
+1 502 ;
+1 503 ; This flag determines if memory is allocated for the semaphore FIFOs or not.
+1 504 ; If set to 0, then no wait for a semaphore is possible. Associated calls
+1 505 ; will return a NOT_OK in this case.
+1 506 ; Set ?RTX_SEMAPHORE_SUPPORT to 0 if semaphore services are not desired.
+1 507 ; Set ?RTX_SEMAPHORE_SUPPORT to 1 if semaphore services are desired.
+1 508 ; (Default is 1)
+1 509 ; NOTE: if an increased XDATA usage compared with RTX-51 V 4.x has to be
+1 510 ; avoided, then this flag should be set to 0 !
+1 511 ;
0001 +1 512 ?RTX_SEMAPHORE_SUPPORT EQU 1
+1 513
+1 514
+1 515 ; 12. IDLE MODE
+1 516 ; =============
+1 517 ;
+1 518 ; If this option is enabled, then each time the RTX idle loop is
+1 519 ; entered the cpu is switched to idle mode. This feature is supported
+1 520 ; for selected cpu's only. enabling it for other cpu's will have no effect.
+1 521 ;
+1 522 ; USE_IDLE = 0: do not use the idle mode
+1 523 ; = 1: set cpu to idle mode during system idle time
+1 524
0000 +1 525 ?RTX_USE_IDLE EQU 0
+1 526
+1 527
+1 528 ;*----------------------------------------------------------------------*
+1 529 ;* END of INCLUDE FILE RTXSETUP.INC *
+1 530
531
532
533 ;========================================================================
534 ; END OF USER-CONFIGURABLE SECTION
535 ;========================================================================
536
537
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 8
538 $eject
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 11/23/2000 06:45:53 PAGE 9
539 ;************************************************************************
540 ;* *
541 ;* THE FOLLOWING SECTIONS MUST NORMALLY NOT BE ALTERED BY THE USER *
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