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FPGA直接读取SD卡扇区数据

without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------------------------------------------------------------+----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+
; Type                                                        ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                            ; To                                                                                                                              ; From Clock                                   ; To Clock                                     ; Failed Paths ;
+-------------------------------------------------------------+----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+
; Worst-case tsu                                              ; N/A      ; None                             ; 7.094 ns                         ; miso_i                                                                                                                          ; spiMaster:u_spiMaster|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0]                                             ; --                                           ; clk0                                         ; 0            ;
; Worst-case tco                                              ; N/A      ; None                             ; 8.205 ns                         ; spiMaster:u_spiMaster|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut                                                     ; sck_o                                                                                                                           ; clk0                                         ; --                                           ; 0            ;
; Worst-case tpd                                              ; N/A      ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                        ; altera_reserved_tdo                                                                                                             ; --                                           ; --                                           ; 0            ;
; Worst-case th                                               ; N/A      ; None                             ; 2.999 ns                         ; altera_internal_jtag~TDIUTAP                                                                                                    ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]                                                                                     ; --                                           ; altera_internal_jtag~TCKUTAP                 ; 0            ;
; Clock Setup: 'clk0'                                         ; 0.364 ns ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; spiMaster:u_spiMaster|ctrlStsRegBI:u_ctrlStsRegBI|spiClkDelay[1]                                                                ; spiMaster:u_spiMaster|initSD:u_initSD|spiClkDelayOut[1]                                                                         ; aaa:clk_module|altpll:altpll_component|_clk0 ; clk0                                         ; 0            ;
; Clock Setup: 'aaa:clk_module|altpll:altpll_component|_clk0' ; 0.537 ns ; 40.00 MHz ( period = 24.999 ns ) ; N/A                              ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndex[2]                                               ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndexSyncToRdClk[2]                                    ; clk0                                         ; aaa:clk_module|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                 ; 3.524 ns ; 50.00 MHz ( period = 20.000 ns ) ; 77.21 MHz ( period = 12.952 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode                                                                                            ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                ; altera_internal_jtag~TCKUTAP                 ; altera_internal_jtag~TCKUTAP                 ; 0            ;
; Clock Hold: 'aaa:clk_module|altpll:altpll_component|_clk0'  ; 0.822 ns ; 40.00 MHz ( period = 24.999 ns ) ; N/A                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] ; aaa:clk_module|altpll:altpll_component|_clk0 ; aaa:clk_module|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'clk0'                                          ; 0.822 ns ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; spiMaster:u_spiMaster|readWriteSPIWireData:u_readWriteSPIWireData|txDataShiftReg[0]                                             ; spiMaster:u_spiMaster|readWriteSPIWireData:u_readWriteSPIWireData|txDataShiftReg[0]                                             ; clk0                                         ; clk0                                         ; 0            ;
; Clock Hold: 'altera_internal_jtag~TCKUTAP'                  ; 0.847 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4]                                                                      ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3]                                                                      ; altera_internal_jtag~TCKUTAP                 ; altera_internal_jtag~TCKUTAP                 ; 0            ;
; Total number of failed paths                                ;          ;                                  ;                                  ;                                                                                                                                 ;                                                                                                                                 ;                                              ;                                              ; 0            ;
+-------------------------------------------------------------+----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;