top.hif

FPGA直接读取SD卡扇区数据

5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
src|sd_RTL|spiMaster_defines.v
a3601ddd731629f47982681dea96a436
}
# hierarchies {
spiMaster:u_spiMaster|initSD:u_initSD
}
# macro_sequence
START4'b0000INIT_NO_ERROR2'b00WT_INIT_REQ4'b0001WT_INIT_REQ4'b0001CLK_SEQ_SEND_FF4'b0010SLOW_SPI_CLK8'h3bINIT_NO_ERROR2'b00CLK_SEQ_SEND_FF4'b0010CLK_SEQ_CHK_FIN4'b0011CLK_SEQ_CHK_FIN4'b0011SD_INIT_START_SEQ_LEN8'ha0CLK_SEQ_WT_DATA_EMPTY4'b1101CLK_SEQ_SEND_FF4'b0010CLK_SEQ_WT_DATA_EMPTY4'b1101RESET_SEND_CMD4'b0100RESET_SEND_CMD4'b0100RESET_DEL4'b0101RESET_DEL4'b0101RESET_WT_FIN4'b0110RESET_WT_FIN4'b0110RESET_CHK_FIN4'b0111RESET_CHK_FIN4'b0111RESET_SEND_CMD4'b0100WT_INIT_REQ4'b0001INIT_CMD0_ERROR2'b01INIT_SEND_CMD4'b1010INIT_WT_FIN4'b1000INIT_CHK_FIN4'b1001INIT_CHK_FIN4'b1001INIT_SEND_CMD4'b1010WT_INIT_REQ4'b0001INIT_CMD1_ERROR2'b10WT_INIT_REQ4'b0001INIT_SEND_CMD4'b1010INIT_DEL14'b1011INIT_DEL14'b1011TWO_MS10'h177INIT_WT_FIN4'b1000INIT_DEL24'b1100INIT_DEL24'b1100INIT_DEL14'b1011START4'b0000INIT_NO_ERROR2'b00
# end
# entity
readWriteSDBlock
# storage
db|top.(8).cnf
db|top.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|readWriteSDBlock.v
9a5d50fb2dacebfd67258f9cf4e94ea0
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
src|sd_RTL|spiMaster_defines.v
a3601ddd731629f47982681dea96a436
}
# hierarchies {
spiMaster:u_spiMaster|readWriteSDBlock:u_readWriteSDBlock
}
# macro_sequence
ST_RW_SD6'b000000READ_NO_ERROR2'b00WRITE_NO_ERROR2'b00WT_REQ6'b000100WT_REQ6'b000100READ_SD_BLOCK2'b10RD_CMD_SEND_CMD6'b010111READ_NO_ERROR2'b00WRITE_SD_BLOCK2'b01WR_CMD_SEND_CMD6'b000001WRITE_NO_ERROR2'b00WR_CMD_SEND_CMD6'b000001WR_CMD_DEL6'b000011WR_CMD_WT_FIN6'b000010WT_REQ6'b000100WRITE_CMD_ERROR2'b01WR_TOKEN_FF1_ST6'b000110WR_CMD_DEL6'b000011WR_CMD_WT_FIN6'b000010WR_TOKEN_FF1_FIN6'b000101WR_TOKEN_FF2_ST6'b001000WR_TOKEN_FF1_ST6'b000110WR_TOKEN_FF1_FIN6'b000101WR_TOKEN_FF2_FIN6'b000111WR_TOKEN_FE_ST6'b001010WR_TOKEN_FF2_ST6'b001000WR_TOKEN_FF2_FIN6'b000111WR_TOKEN_FE_FIN6'b001001WR_DATA_LOOP_INIT6'b001111WR_TOKEN_FE_ST6'b001010WR_TOKEN_FE_FIN6'b001001WR_BUSY_CHK_FIN6'b101000TWO_FIFTY_MS12'h0b6WR_BUSY_SEND_CMD16'b101011TWO_FIFTY_MS12'h0b6WT_REQ6'b000100WRITE_BUSY_ERROR2'b11WT_REQ6'b000100WR_BUSY_WT_FIN16'b101001WR_BUSY_CHK_FIN6'b101000WR_BUSY_DEL16'b101010MAX_8_BIT8'hffWR_BUSY_WT_FIN16'b101001WR_BUSY_DEL26'b101100WR_BUSY_SEND_CMD16'b101011WR_BUSY_DEL16'b101010WR_BUSY_DEL26'b101100WR_BUSY_DEL16'b101010WR_BUSY_INIT_LOOP6'b101101WR_BUSY_SEND_CMD16'b101011RD_CMD_SEND_CMD6'b010111RD_CMD_DEL6'b011001RD_CMD_WT_FIN6'b011000WT_REQ6'b000100READ_CMD_ERROR2'b01RD_TOKEN_INIT_LOOP6'b011110RD_CMD_DEL6'b011001RD_CMD_WT_FIN6'b011000RD_TOKEN_CHK_LOOP6'b011010ONE_HUNDRED_MS12'h048RD_TOKEN_DEL26'b011101ONE_HUNDRED_MS12'h048WT_REQ6'b000100READ_TOKEN_ERROR2'b10RD_DATA_CLR_RX6'b100011RD_TOKEN_WT_FIN6'b011011RD_TOKEN_CHK_LOOP6'b011010RD_TOKEN_SEND_CMD6'b011100RD_TOKEN_DEL16'b011111RD_TOKEN_DEL26'b011101MAX_8_BIT8'hffRD_TOKEN_SEND_CMD6'b011100RD_TOKEN_DEL36'b101110RD_TOKEN_INIT_LOOP6'b011110RD_TOKEN_SEND_CMD6'b011100RD_TOKEN_DEL16'b011111RD_TOKEN_WT_FIN6'b011011RD_TOKEN_DEL36'b101110RD_TOKEN_DEL26'b011101RD_DATA_ST_LOOP6'b100000RD_DATA_WT_DATA6'b100001RD_DATA_WT_DATA6'b100001RD_DATA_CHK_LOOP6'b100010RD_DATA_CHK_LOOP6'b100010RD_DATA_CS_ST16'b100110RD_DATA_ST_LOOP6'b100000RD_DATA_CLR_RX6'b100011RD_DATA_ST_LOOP6'b100000RD_DATA_CS_FIN26'b100100WT_REQ6'b000100RD_DATA_CS_FIN16'b100101RD_DATA_CS_ST26'b100111RD_DATA_CS_ST16'b100110RD_DATA_CS_FIN16'b100101RD_DATA_CS_ST26'b100111RD_DATA_CS_FIN26'b100100WR_DATA_D_FIN6'b001011WR_DATA_CS_ST16'b010000WR_DATA_RD_FIFO16'b001101WR_DATA_D_ST6'b001100WR_DATA_D_FIN6'b001011WR_DATA_RD_FIFO16'b001101WR_DATA_RD_FIFO26'b001110WR_DATA_RD_FIFO26'b001110WR_DATA_D_ST6'b001100WR_DATA_LOOP_INIT6'b001111WR_DATA_RD_FIFO16'b001101WR_DATA_CS_ST16'b010000WR_DATA_CS_FIN16'b010001WR_DATA_CS_FIN16'b010001WR_DATA_CS_ST26'b010011WR_DATA_CS_FIN26'b010010WR_DATA_REQ_RESP_ST6'b010101WR_DATA_CS_ST26'b010011WR_DATA_CS_FIN26'b010010WR_DATA_CHK_RESP6'b010100WR_RESP_TOUT12'hf00WT_REQ6'b000100WRITE_DATA_ERROR2'b10WR_BUSY_INIT_LOOP6'b101101WR_DATA_REQ_RESP_ST6'b010101WR_DATA_REQ_RESP_ST6'b010101WR_DATA_DEL6'b101111WR_DATA_REQ_RESP_FIN6'b010110WR_DATA_CHK_RESP6'b010100WR_DATA_DEL6'b101111WR_DATA_REQ_RESP_FIN6'b010110ST_RW_SD6'b000000
# end
# entity
sendCmd
# storage
db|top.(9).cnf
db|top.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|sendCmd.v
9494a3722f48b6276b383968037749
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:u_spiMaster|sendCmd:u_sendCmd
}
# macro_sequence
WT_CMD5'b10001CMD_SEND_FF_ST5'b01111ST_S_CMD5'b10010WT_CMD5'b10001CMD_D_BYTE2_FIN5'b00000CMD_D_BYTE3_ST5'b01010CMD_D_BYTE2_ST5'b00001CMD_D_BYTE2_FIN5'b00000CMD_SEND_FF_FIN5'b00010CMD_CMD_BYTE_ST5'b10000CMD_CMD_BYTE_FIN5'b00011CMD_D_BYTE1_ST5'b01000CMD_D_BYTE1_FIN5'b00100CMD_D_BYTE2_ST5'b00001CMD_REQ_RESP_ST5'b00101CMD_DEL5'b10011CMD_REQ_RESP_FIN5'b00110CMD_CHK_RESP5'b00111CMD_CHK_RESP5'b00111WT_CMD5'b10001WT_CMD5'b10001CMD_REQ_RESP_ST5'b00101CMD_D_BYTE1_ST5'b01000CMD_D_BYTE1_FIN5'b00100CMD_D_BYTE3_FIN5'b01001CMD_D_BYTE4_ST5'b01100CMD_D_BYTE3_ST5'b01010CMD_D_BYTE3_FIN5'b01001CMD_D_BYTE4_FIN5'b01011CMD_CS_ST5'b01110CMD_D_BYTE4_ST5'b01100CMD_D_BYTE4_FIN5'b01011CMD_CS_FIN5'b01101CMD_REQ_RESP_ST5'b00101CMD_CS_ST5'b01110CMD_CS_FIN5'b01101CMD_SEND_FF_ST5'b01111CMD_SEND_FF_FIN5'b00010CMD_CMD_BYTE_ST5'b10000CMD_CMD_BYTE_FIN5'b00011CMD_DEL5'b10011CMD_REQ_RESP_FIN5'b00110ST_S_CMD5'b10010
# end
# entity
spiTxRxData
# storage
db|top.(10).cnf
db|top.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|spiTxRxData.v
5ac4a27e239c4f08a293c6951b7fe37
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
spiMaster:u_spiMaster|spiTxRxData:u_spiTxRxData
}
# macro_sequence

# end
# entity
readWriteSPIWireData
# storage
db|top.(11).cnf
db|top.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|readWriteSPIWireData.v
d0318c89a646c1ce19e9ccb646a652cd
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
src|sd_RTL|spiMaster_defines.v
a3601ddd731629f47982681dea96a436
}
# hierarchies {
spiMaster:u_spiMaster|readWriteSPIWireData:u_readWriteSPIWireData
}
# macro_sequence
WT_TX_DATA2'b00CLK_HI2'b01CLK_HI2'b01CLK_LO2'b10CLK_LO2'b10CLK_HI2'b01WT_TX_DATA2'b00CLK_HI2'b01ST_RW_WIRE2'b11WT_TX_DATA2'b00ST_RW_WIRE2'b11
# end
# entity
sm_TxFifo
# storage
db|top.(12).cnf
db|top.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|sm_TxFifo.v
36498515a2a01902bb6d14416b37ae3
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FIFO_DEPTH
512
PARAMETER_SIGNED_DEC
USR
ADDR_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:u_spiMaster|sm_TxFifo:u_sm_txFifo
}
# macro_sequence

# end
# entity
sm_fifoRTL
# storage
db|top.(13).cnf
db|top.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|sm_fifoRTL.v
2cfa5b4bff721295f0b18db1cedadf4c
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FIFO_WIDTH
8
PARAMETER_SIGNED_DEC
USR
FIFO_DEPTH
512
PARAMETER_SIGNED_DEC
USR
ADDR_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:u_spiMaster|sm_TxFifo:u_sm_txFifo|sm_fifoRTL:u_sm_fifo
spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo
}
# macro_sequence

# end
# entity
sm_dpMem_dc
# storage
db|top.(14).cnf
db|top.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|sm_dpMem_dc.v
b32e06267d868d4b23afb4b7b4eb3c
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FIFO_WIDTH
8
PARAMETER_SIGNED_DEC
USR
FIFO_DEPTH
512
PARAMETER_SIGNED_DEC
USR
ADDR_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:u_spiMaster|sm_TxFifo:u_sm_txFifo|sm_fifoRTL:u_sm_fifo|sm_dpMem_dc:u_sm_dpMem_dc
spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|sm_dpMem_dc:u_sm_dpMem_dc
}
# macro_sequence

# end
# entity
sm_TxfifoBI
# storage
db|top.(15).cnf
db|top.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|sm_TxFifoBI.v
2bafb12717d07440dea6a6f7dbff55ae
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
src|sd_RTL|spiMaster_defines.v
a3601ddd731629f47982681dea96a436
}
# hierarchies {
spiMaster:u_spiMaster|sm_TxFifo:u_sm_txFifo|sm_TxfifoBI:u_sm_TxfifoBI
}
# macro_sequence
FIFO_CONTROL_REG3'b100FIFO_DATA_REG3'b000
# end
# entity
sm_RxFifo
# storage
db|top.(16).cnf
db|top.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|sm_RxFifo.v
dde4bbf1d8223fc7c0247aa86bbc4948
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FIFO_DEPTH
512
PARAMETER_SIGNED_DEC
USR
ADDR_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo
}
# macro_sequence

# end
# entity
sm_RxfifoBI
# storage
db|top.(17).cnf
db|top.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|sd_RTL|sm_RxFifoBI.v
4027b14145e9be0c217c747cb02258
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
src|sd_RTL|timescale.v
90acbbce5b36e269c098dfecb82797
src|sd_RTL|spiMaster_defines.v
a3601ddd731629f47982681dea96a436
}
# hierarchies {
spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_RxfifoBI:u_sm_RxfifoBI
}
# macro_sequence
FIFO_CONTROL_REG3'b100FIFO_DATA_REG3'b000FIFO_DATA_COUNT_MSB3'b010FIFO_DATA_COUNT_LSB3'b011FIFO_DATA_REG3'b000
# end
# entity
tc_top
# storage
db|top.(19).cnf
db|top.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|wishbone|tc_top.v
e8f2839e42d78b1b19199a36ea048
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
t_addr_w
8
PARAMETER_SIGNED_DEC
USR
t0_addr
10010010
PARAMETER_UNSIGNED_BIN
USR
t1_addr
0001
PARAMETER_UNSIGNED_BIN
DEF
t2_addr
0010
PARAMETER_UNSIGNED_BIN
DEF
t3_addr
0011
PARAMETER_UNSIGNED_BIN
DEF
t4_addr
0100
PARAMETER_UNSIGNED_BIN
DEF
t5_addr
0101
PARAMETER_UNSIGNED_BIN
DEF
t6_addr
0110
PARAMETER_UNSIGNED_BIN
DEF
t7_addr
0111
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
src|wishbone|tc_define.v
1bfa50e059ab50b0cfcc10eff0fccc78
}
# hierarchies {
tc_top:tc_top
}
# macro_sequence
TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32
# end
# entity
tc_mi_to_st
# storage
db|top.(20).cnf
db|top.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|wishbone|tc_mi_to_st.v
eba7dd40a1c3721507bdf92dda3ae9
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
src|wishbone|tc_define.v
1bfa50e059ab50b0cfcc10eff0fccc78
}
# hierarchies {
tc_top:tc_top|tc_mi_to_st:t07_ch_upper
}
# macro_sequence
TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32
# end
# entity
tc_si_to_mt
# storage
db|top.(21).cnf
db|top.(21).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|wishbone|tc_si_to_mt.v
37c3daa8db41dddb2d9cc4afe46bd89
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
t_addr_w
8
PARAMETER_SIGNED_DEC
USR
t0_addr
10010010
PARAMETER_UNSIGNED_BIN
USR
t1_addr
0001
PARAMETER_UNSIGNED_BIN
USR
t2_addr
0010
PARAMETER_UNSIGNED_BIN
USR
t3_addr
0011
PARAMETER_UNSIGNED_BIN
USR
t4_addr
0100
PARAMETER_UNSIGNED_BIN
USR
t5_addr
0101
PARAMETER_UNSIGNED_BIN
USR
t6_addr
0110
PARAMETER_UNSIGNED_BIN
USR
t7_addr
0111
PARAMETER_UNSIGNED_BIN
USR
}
# include_file {
src|wishbone|tc_define.v
1bfa50e059ab50b0cfcc10eff0fccc78
}
# hierarchies {
tc_top:tc_top|tc_si_to_mt:t18_ch_lower
}
# macro_sequence
TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_AW32TC_BSW4TC_DW32TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_IIN_W1+1+1+`TC_AW+`TC_BSW+1+`TC_DWTC_AW32TC_BSW4TC_DW32TC_TIN_W`TC_DW+1+1TC_DW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32TC_AW32
# end
# entity
sld_signaltap
# storage
db|top.(22).cnf
db|top.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_signaltap.vhd
b7ac8140a71dfdb7f372588a23bd
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
18
PARAMETER_UNKNOWN
USR
sld_trigger_bits
18
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
26243
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
30327
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
SLD_RAM_BLOCK_TYPE
AUTO
PARAMETER_STRING
DEF
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
1
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
79
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|top.(23).cnf
db|top.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_signaltap.vhd
b7ac8140a71dfdb7f372588a23bd
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version