top.hier_info

FPGA直接读取SD卡扇区数据

dataByte4[4] <= dataByte4[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataByte4[5] <= dataByte4[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataByte4[6] <= dataByte4[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataByte4[7] <= dataByte4[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
initError[0] <= initError[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
initError[1] <= initError[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
respByte[0] => Equal2.IN0
respByte[0] => Equal3.IN0
respByte[1] => Equal2.IN1
respByte[1] => Equal3.IN1
respByte[2] => Equal2.IN2
respByte[2] => Equal3.IN2
respByte[3] => Equal2.IN3
respByte[3] => Equal3.IN3
respByte[4] => Equal2.IN4
respByte[4] => Equal3.IN4
respByte[5] => Equal2.IN5
respByte[5] => Equal3.IN5
respByte[6] => Equal2.IN6
respByte[6] => Equal3.IN6
respByte[7] => Equal2.IN7
respByte[7] => Equal3.IN7
respTout => always0~3.IN0
respTout => always0~1.IN1
rst => delCnt2~7.OUTPUTSELECT
rst => delCnt2~6.OUTPUTSELECT
rst => delCnt2~5.OUTPUTSELECT
rst => delCnt2~4.OUTPUTSELECT
rst => delCnt2~3.OUTPUTSELECT
rst => delCnt2~2.OUTPUTSELECT
rst => delCnt2~1.OUTPUTSELECT
rst => delCnt2~0.OUTPUTSELECT
rst => delCnt1~9.OUTPUTSELECT
rst => delCnt1~8.OUTPUTSELECT
rst => delCnt1~7.OUTPUTSELECT
rst => delCnt1~6.OUTPUTSELECT
rst => delCnt1~5.OUTPUTSELECT
rst => delCnt1~4.OUTPUTSELECT
rst => delCnt1~3.OUTPUTSELECT
rst => delCnt1~2.OUTPUTSELECT
rst => delCnt1~1.OUTPUTSELECT
rst => delCnt1~0.OUTPUTSELECT
rst => loopCnt~7.OUTPUTSELECT
rst => loopCnt~6.OUTPUTSELECT
rst => loopCnt~5.OUTPUTSELECT
rst => loopCnt~4.OUTPUTSELECT
rst => loopCnt~3.OUTPUTSELECT
rst => loopCnt~2.OUTPUTSELECT
rst => loopCnt~1.OUTPUTSELECT
rst => loopCnt~0.OUTPUTSELECT
rst => rxDataRdyClr~0.OUTPUTSELECT
rst => sendCmdReq~0.OUTPUTSELECT
rst => checkSumByte~7.OUTPUTSELECT
rst => checkSumByte~6.OUTPUTSELECT
rst => checkSumByte~5.OUTPUTSELECT
rst => checkSumByte~4.OUTPUTSELECT
rst => checkSumByte~3.OUTPUTSELECT
rst => checkSumByte~2.OUTPUTSELECT
rst => checkSumByte~1.OUTPUTSELECT
rst => checkSumByte~0.OUTPUTSELECT
rst => dataByte4~7.OUTPUTSELECT
rst => dataByte4~6.OUTPUTSELECT
rst => dataByte4~5.OUTPUTSELECT
rst => dataByte4~4.OUTPUTSELECT
rst => dataByte4~3.OUTPUTSELECT
rst => dataByte4~2.OUTPUTSELECT
rst => dataByte4~1.OUTPUTSELECT
rst => dataByte4~0.OUTPUTSELECT
rst => dataByte3~7.OUTPUTSELECT
rst => dataByte3~6.OUTPUTSELECT
rst => dataByte3~5.OUTPUTSELECT
rst => dataByte3~4.OUTPUTSELECT
rst => dataByte3~3.OUTPUTSELECT
rst => dataByte3~2.OUTPUTSELECT
rst => dataByte3~1.OUTPUTSELECT
rst => dataByte3~0.OUTPUTSELECT
rst => dataByte2~7.OUTPUTSELECT
rst => dataByte2~6.OUTPUTSELECT
rst => dataByte2~5.OUTPUTSELECT
rst => dataByte2~4.OUTPUTSELECT
rst => dataByte2~3.OUTPUTSELECT
rst => dataByte2~2.OUTPUTSELECT
rst => dataByte2~1.OUTPUTSELECT
rst => dataByte2~0.OUTPUTSELECT
rst => dataByte1~7.OUTPUTSELECT
rst => dataByte1~6.OUTPUTSELECT
rst => dataByte1~5.OUTPUTSELECT
rst => dataByte1~4.OUTPUTSELECT
rst => dataByte1~3.OUTPUTSELECT
rst => dataByte1~2.OUTPUTSELECT
rst => dataByte1~1.OUTPUTSELECT
rst => dataByte1~0.OUTPUTSELECT
rst => cmdByte~7.OUTPUTSELECT
rst => cmdByte~6.OUTPUTSELECT
rst => cmdByte~5.OUTPUTSELECT
rst => cmdByte~4.OUTPUTSELECT
rst => cmdByte~3.OUTPUTSELECT
rst => cmdByte~2.OUTPUTSELECT
rst => cmdByte~1.OUTPUTSELECT
rst => cmdByte~0.OUTPUTSELECT
rst => txDataWen~0.OUTPUTSELECT
rst => txDataOut~7.OUTPUTSELECT
rst => txDataOut~6.OUTPUTSELECT
rst => txDataOut~5.OUTPUTSELECT
rst => txDataOut~4.OUTPUTSELECT
rst => txDataOut~3.OUTPUTSELECT
rst => txDataOut~2.OUTPUTSELECT
rst => txDataOut~1.OUTPUTSELECT
rst => txDataOut~0.OUTPUTSELECT
rst => initError~1.OUTPUTSELECT
rst => initError~0.OUTPUTSELECT
rst => spiCS_n~0.OUTPUTSELECT
rst => SDInitRdy~0.OUTPUTSELECT
rst => spiClkDelayOut~7.OUTPUTSELECT
rst => spiClkDelayOut~6.OUTPUTSELECT
rst => spiClkDelayOut~5.OUTPUTSELECT
rst => spiClkDelayOut~4.OUTPUTSELECT
rst => spiClkDelayOut~3.OUTPUTSELECT
rst => spiClkDelayOut~2.OUTPUTSELECT
rst => spiClkDelayOut~1.OUTPUTSELECT
rst => spiClkDelayOut~0.OUTPUTSELECT
rst => CurrState_initSDSt~13.OUTPUTSELECT
rst => CurrState_initSDSt~12.OUTPUTSELECT
rst => CurrState_initSDSt~11.OUTPUTSELECT
rst => CurrState_initSDSt~10.OUTPUTSELECT
rst => CurrState_initSDSt~9.OUTPUTSELECT
rst => CurrState_initSDSt~8.OUTPUTSELECT
rst => CurrState_initSDSt~7.OUTPUTSELECT
rst => CurrState_initSDSt~6.OUTPUTSELECT
rst => CurrState_initSDSt~5.OUTPUTSELECT
rst => CurrState_initSDSt~4.OUTPUTSELECT
rst => CurrState_initSDSt~3.OUTPUTSELECT
rst => CurrState_initSDSt~2.OUTPUTSELECT
rst => CurrState_initSDSt~1.OUTPUTSELECT
rst => CurrState_initSDSt~0.OUTPUTSELECT
rxDataRdy => ~NO_FANOUT~
rxDataRdyClr <= rxDataRdyClr~reg0.DB_MAX_OUTPUT_PORT_TYPE
SDInitRdy <= SDInitRdy~reg0.DB_MAX_OUTPUT_PORT_TYPE
SDInitReq => next_initError~1.OUTPUTSELECT
SDInitReq => next_initError~0.OUTPUTSELECT
SDInitReq => next_spiClkDelayOut~7.OUTPUTSELECT
SDInitReq => next_spiClkDelayOut~6.OUTPUTSELECT
SDInitReq => next_spiClkDelayOut~5.OUTPUTSELECT
SDInitReq => next_spiClkDelayOut~4.OUTPUTSELECT
SDInitReq => next_spiClkDelayOut~3.OUTPUTSELECT
SDInitReq => next_spiClkDelayOut~2.OUTPUTSELECT
SDInitReq => next_spiClkDelayOut~1.OUTPUTSELECT
SDInitReq => next_spiClkDelayOut~0.OUTPUTSELECT
SDInitReq => next_loopCnt~7.OUTPUTSELECT
SDInitReq => next_loopCnt~6.OUTPUTSELECT
SDInitReq => next_loopCnt~5.OUTPUTSELECT
SDInitReq => next_loopCnt~4.OUTPUTSELECT
SDInitReq => next_loopCnt~3.OUTPUTSELECT
SDInitReq => next_loopCnt~2.OUTPUTSELECT
SDInitReq => next_loopCnt~1.OUTPUTSELECT
SDInitReq => next_loopCnt~0.OUTPUTSELECT
SDInitReq => NextState_initSDSt~13.OUTPUTSELECT
SDInitReq => NextState_initSDSt~12.OUTPUTSELECT
SDInitReq => NextState_initSDSt~11.OUTPUTSELECT
SDInitReq => NextState_initSDSt~10.OUTPUTSELECT
SDInitReq => NextState_initSDSt~9.OUTPUTSELECT
SDInitReq => NextState_initSDSt~8.OUTPUTSELECT
SDInitReq => NextState_initSDSt~7.OUTPUTSELECT
SDInitReq => NextState_initSDSt~6.OUTPUTSELECT
SDInitReq => NextState_initSDSt~5.OUTPUTSELECT
SDInitReq => NextState_initSDSt~4.OUTPUTSELECT
SDInitReq => NextState_initSDSt~3.OUTPUTSELECT
SDInitReq => NextState_initSDSt~2.OUTPUTSELECT
SDInitReq => NextState_initSDSt~1.OUTPUTSELECT
SDInitReq => NextState_initSDSt~0.OUTPUTSELECT
SDInitReq => Selector8.IN1
sendCmdRdy => NextState_initSDSt~59.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~58.OUTPUTSELECT
sendCmdRdy => next_spiCS_n~0.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~55.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~54.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~53.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~52.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~51.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~50.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~49.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~48.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~47.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~46.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~45.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~44.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~43.OUTPUTSELECT
sendCmdRdy => NextState_initSDSt~42.OUTPUTSELECT
sendCmdReq <= sendCmdReq~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiClkDelayIn[0] => spiClkDelayOut~7.DATAB
spiClkDelayIn[0] => Selector7.IN2
spiClkDelayIn[0] => next_spiClkDelayOut~7.DATAA
spiClkDelayIn[1] => spiClkDelayOut~6.DATAB
spiClkDelayIn[1] => Selector6.IN2
spiClkDelayIn[1] => next_spiClkDelayOut~6.DATAA
spiClkDelayIn[2] => spiClkDelayOut~5.DATAB
spiClkDelayIn[2] => Selector5.IN2
spiClkDelayIn[2] => next_spiClkDelayOut~5.DATAA
spiClkDelayIn[3] => spiClkDelayOut~4.DATAB
spiClkDelayIn[3] => Selector4.IN2
spiClkDelayIn[3] => next_spiClkDelayOut~4.DATAA
spiClkDelayIn[4] => spiClkDelayOut~3.DATAB
spiClkDelayIn[4] => Selector3.IN2
spiClkDelayIn[4] => next_spiClkDelayOut~3.DATAA
spiClkDelayIn[5] => spiClkDelayOut~2.DATAB
spiClkDelayIn[5] => Selector2.IN2
spiClkDelayIn[5] => next_spiClkDelayOut~2.DATAA
spiClkDelayIn[6] => spiClkDelayOut~1.DATAB
spiClkDelayIn[6] => Selector1.IN2
spiClkDelayIn[6] => next_spiClkDelayOut~1.DATAA
spiClkDelayIn[7] => spiClkDelayOut~0.DATAB
spiClkDelayIn[7] => Selector0.IN2
spiClkDelayIn[7] => next_spiClkDelayOut~0.DATAA
spiClkDelayOut[0] <= spiClkDelayOut[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiClkDelayOut[1] <= spiClkDelayOut[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiClkDelayOut[2] <= spiClkDelayOut[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiClkDelayOut[3] <= spiClkDelayOut[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiClkDelayOut[4] <= spiClkDelayOut[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiClkDelayOut[5] <= spiClkDelayOut[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiClkDelayOut[6] <= spiClkDelayOut[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiClkDelayOut[7] <= spiClkDelayOut[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spiCS_n <= spiCS_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataEmpty => next_loopCnt~23.OUTPUTSELECT
txDataEmpty => next_loopCnt~22.OUTPUTSELECT
txDataEmpty => next_loopCnt~21.OUTPUTSELECT
txDataEmpty => next_loopCnt~20.OUTPUTSELECT
txDataEmpty => next_loopCnt~19.OUTPUTSELECT
txDataEmpty => next_loopCnt~18.OUTPUTSELECT
txDataEmpty => next_loopCnt~17.OUTPUTSELECT
txDataEmpty => next_loopCnt~16.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~41.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~40.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~39.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~38.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~37.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~36.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~35.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~34.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~33.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~32.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~31.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~30.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~29.OUTPUTSELECT
txDataEmpty => NextState_initSDSt~28.OUTPUTSELECT
txDataFull => next_loopCnt~15.OUTPUTSELECT
txDataFull => next_loopCnt~14.OUTPUTSELECT
txDataFull => next_loopCnt~13.OUTPUTSELECT
txDataFull => next_loopCnt~12.OUTPUTSELECT
txDataFull => next_loopCnt~11.OUTPUTSELECT
txDataFull => next_loopCnt~10.OUTPUTSELECT
txDataFull => next_loopCnt~9.OUTPUTSELECT
txDataFull => next_loopCnt~8.OUTPUTSELECT
txDataFull => next_txDataWen~0.OUTPUTSELECT
txDataFull => next_txDataOut~7.OUTPUTSELECT
txDataFull => next_txDataOut~6.OUTPUTSELECT
txDataFull => next_txDataOut~5.OUTPUTSELECT
txDataFull => next_txDataOut~4.OUTPUTSELECT
txDataFull => next_txDataOut~3.OUTPUTSELECT
txDataFull => next_txDataOut~2.OUTPUTSELECT
txDataFull => next_txDataOut~1.OUTPUTSELECT
txDataFull => next_txDataOut~0.OUTPUTSELECT
txDataFull => NextState_initSDSt~27.OUTPUTSELECT
txDataFull => NextState_initSDSt~26.OUTPUTSELECT
txDataFull => NextState_initSDSt~25.OUTPUTSELECT
txDataFull => NextState_initSDSt~24.OUTPUTSELECT
txDataFull => NextState_initSDSt~23.OUTPUTSELECT
txDataFull => NextState_initSDSt~22.OUTPUTSELECT
txDataFull => NextState_initSDSt~21.OUTPUTSELECT
txDataFull => NextState_initSDSt~20.OUTPUTSELECT
txDataFull => NextState_initSDSt~19.OUTPUTSELECT
txDataFull => NextState_initSDSt~18.OUTPUTSELECT
txDataFull => NextState_initSDSt~17.OUTPUTSELECT
txDataFull => NextState_initSDSt~16.OUTPUTSELECT
txDataFull => NextState_initSDSt~15.OUTPUTSELECT
txDataFull => NextState_initSDSt~14.OUTPUTSELECT
txDataOut[0] <= txDataOut[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataOut[1] <= txDataOut[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataOut[2] <= txDataOut[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataOut[3] <= txDataOut[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataOut[4] <= txDataOut[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataOut[5] <= txDataOut[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataOut[6] <= txDataOut[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataOut[7] <= txDataOut[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
txDataWen <= txDataWen~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top|spiMaster:u_spiMaster|readWriteSDBlock:u_readWriteSDBlock
blockAddr[0] => Selector51.IN4
blockAddr[1] => Selector50.IN4
blockAddr[2] => Selector49.IN4
blockAddr[3] => Selector48.IN4
blockAddr[4] => Selector47.IN4
blockAddr[5] => Selector46.IN4
blockAddr[6] => Selector45.IN4
blockAddr[7] => Selector44.IN4
blockAddr[8] => Selector43.IN4
blockAddr[9] => Selector42.IN4
blockAddr[10] => Selector41.IN4
blockAddr[11] => Selector40.IN4
blockAddr[12] => Selector39.IN4
blockAddr[13] => Selector38.IN4
blockAddr[14] => Selector37.IN4
blockAddr[15] => Selector36.IN4
blockAddr[16] => Selector35.IN4
blockAddr[17] => Selector34.IN4
blockAddr[18] => Selector33.IN4
blockAddr[19] => Selector32.IN4
blockAddr[20] => Selector31.IN4
blockAddr[21] => Selector30.IN4
blockAddr[22] => Selector29.IN4
blockAddr[23] => Selector28.IN4
blockAddr[24] => Selector27.IN4
blockAddr[25] => Selector26.IN4
blockAddr[26] => Selector25.IN4
blockAddr[27] => Selector24.IN4
blockAddr[28] => Selector23.IN4
blockAddr[29] => Selector22.IN4
blockAddr[30] => Selector21.IN4
blockAddr[31] => Selector20.IN4
checkSumByte[0] <= checkSumByte[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
checkSumByte[1] <= checkSumByte[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
checkSumByte[2] <= checkSumByte[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
checkSumByte[3] <= checkSumByte[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
checkSumByte[4] <= checkSumByte[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
checkSumByte[5] <= checkSumByte[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
checkSumByte[6] <= checkSumByte[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
checkSumByte[7] <= checkSumByte[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => readWriteSDBlockRdy~reg0.CLK