top.hier_info

FPGA直接读取SD卡扇区数据

|top
clk0 => clk0~0.IN2
rstn => rst_r.PRESET
led <= ctrl_eth:ctrl_eth.led
sck_o <= spiMaster:u_spiMaster.spiClkOut
mosi_o <= spiMaster:u_spiMaster.spiDataOut
miso_i => miso_i~0.IN1
csn_o <= spiMaster:u_spiMaster.spiCS_n


|top|aaa:clk_module
inclk0 => sub_wire4[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk


|top|aaa:clk_module|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~2.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1]~1.DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|top|spiMaster:u_spiMaster
clk_i => clk_i~0.IN4
rst_i => rst_i~0.IN2
address_i[0] => address_i[0]~7.IN4
address_i[1] => address_i[1]~6.IN4
address_i[2] => address_i[2]~5.IN4
address_i[3] => address_i[3]~4.IN2
address_i[4] => address_i[4]~3.IN2
address_i[5] => address_i[5]~2.IN2
address_i[6] => address_i[6]~1.IN2
address_i[7] => address_i[7]~0.IN2
data_i[0] => data_i[0]~7.IN4
data_i[1] => data_i[1]~6.IN4
data_i[2] => data_i[2]~5.IN4
data_i[3] => data_i[3]~4.IN4
data_i[4] => data_i[4]~3.IN4
data_i[5] => data_i[5]~2.IN4
data_i[6] => data_i[6]~1.IN4
data_i[7] => data_i[7]~0.IN4
data_o[0] <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.dataOut
data_o[1] <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.dataOut
data_o[2] <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.dataOut
data_o[3] <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.dataOut
data_o[4] <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.dataOut
data_o[5] <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.dataOut
data_o[6] <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.dataOut
data_o[7] <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.dataOut
strobe_i => strobe_i~0.IN4
we_i => we_i~0.IN4
ack_o <= spiMasterWishBoneBI:u_spiMasterWishBoneBI.ack_o
spiSysClk => spiSysClk~0.IN9
spiClkOut <= readWriteSPIWireData:u_readWriteSPIWireData.spiClkOut
spiDataIn => spiDataIn~0.IN1
spiDataOut <= readWriteSPIWireData:u_readWriteSPIWireData.spiDataOut
spiCS_n <= spiCS_n~1.DB_MAX_OUTPUT_PORT_TYPE


|top|spiMaster:u_spiMaster|spiMasterWishBoneBI:u_spiMasterWishBoneBI
clk => ack_delayed.CLK
rst => ~NO_FANOUT~
address[0] => Equal0.IN1
address[0] => Equal1.IN1
address[1] => Equal0.IN2
address[1] => Equal1.IN2
address[2] => Equal0.IN3
address[2] => Equal1.IN3
address[3] => Equal0.IN4
address[3] => Equal1.IN4
address[4] => Decoder0.IN7
address[4] => Equal0.IN0
address[4] => Equal1.IN5
address[5] => Decoder0.IN6
address[5] => Equal0.IN5
address[5] => Equal1.IN0
address[6] => Decoder0.IN5
address[6] => Equal0.IN6
address[6] => Equal1.IN6
address[7] => Decoder0.IN4
address[7] => Equal0.IN7
address[7] => Equal1.IN7
dataIn[0] => ~NO_FANOUT~
dataIn[1] => ~NO_FANOUT~
dataIn[2] => ~NO_FANOUT~
dataIn[3] => ~NO_FANOUT~
dataIn[4] => ~NO_FANOUT~
dataIn[5] => ~NO_FANOUT~
dataIn[6] => ~NO_FANOUT~
dataIn[7] => ~NO_FANOUT~
dataOut[0] <= Selector7.DB_MAX_OUTPUT_PORT_TYPE
dataOut[1] <= Selector6.DB_MAX_OUTPUT_PORT_TYPE
dataOut[2] <= Selector5.DB_MAX_OUTPUT_PORT_TYPE
dataOut[3] <= Selector4.DB_MAX_OUTPUT_PORT_TYPE
dataOut[4] <= Selector3.DB_MAX_OUTPUT_PORT_TYPE
dataOut[5] <= Selector2.DB_MAX_OUTPUT_PORT_TYPE
dataOut[6] <= Selector1.DB_MAX_OUTPUT_PORT_TYPE
dataOut[7] <= Selector0.DB_MAX_OUTPUT_PORT_TYPE
writeEn => always3~1.IN0
strobe_i => ack_delayed.DATAIN
strobe_i => ack_o~1.DATAA
strobe_i => ack_o~0.IN1
ack_o <= ack_o~1.DB_MAX_OUTPUT_PORT_TYPE
ctrlStsRegSel <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
rxFifoSel <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
txFifoSel <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
dataFromCtrlStsReg[0] => Selector7.IN5
dataFromCtrlStsReg[1] => Selector6.IN5
dataFromCtrlStsReg[2] => Selector5.IN5
dataFromCtrlStsReg[3] => Selector4.IN5
dataFromCtrlStsReg[4] => Selector3.IN5
dataFromCtrlStsReg[5] => Selector2.IN5
dataFromCtrlStsReg[6] => Selector1.IN5
dataFromCtrlStsReg[7] => Selector0.IN5
dataFromRxFifo[0] => Selector7.IN6
dataFromRxFifo[1] => Selector6.IN6
dataFromRxFifo[2] => Selector5.IN6
dataFromRxFifo[3] => Selector4.IN6
dataFromRxFifo[4] => Selector3.IN6
dataFromRxFifo[5] => Selector2.IN6
dataFromRxFifo[6] => Selector1.IN6
dataFromRxFifo[7] => Selector0.IN6
dataFromTxFifo[0] => Selector7.IN7
dataFromTxFifo[1] => Selector6.IN7
dataFromTxFifo[2] => Selector5.IN7
dataFromTxFifo[3] => Selector4.IN7
dataFromTxFifo[4] => Selector3.IN7
dataFromTxFifo[5] => Selector2.IN7
dataFromTxFifo[6] => Selector1.IN7
dataFromTxFifo[7] => Selector0.IN7


|top|spiMaster:u_spiMaster|ctrlStsRegBI:u_ctrlStsRegBI
busClk => spiTransTypeSTB[1].CLK
busClk => spiTransTypeSTB[0].CLK
busClk => spiTransCtrlSTB.CLK
busClk => spiDirectAccessTxDataSTB[7].CLK
busClk => spiDirectAccessTxDataSTB[6].CLK
busClk => spiDirectAccessTxDataSTB[5].CLK
busClk => spiDirectAccessTxDataSTB[4].CLK
busClk => spiDirectAccessTxDataSTB[3].CLK
busClk => spiDirectAccessTxDataSTB[2].CLK
busClk => spiDirectAccessTxDataSTB[1].CLK
busClk => spiDirectAccessTxDataSTB[0].CLK
busClk => spiClkDelay[7]~reg0.CLK
busClk => spiClkDelay[6]~reg0.CLK
busClk => spiClkDelay[5]~reg0.CLK
busClk => spiClkDelay[4]~reg0.CLK
busClk => spiClkDelay[3]~reg0.CLK
busClk => spiClkDelay[2]~reg0.CLK
busClk => spiClkDelay[1]~reg0.CLK
busClk => spiClkDelay[0]~reg0.CLK
busClk => rstFromBus.CLK
busClk => SDAddr[31]~reg0.CLK
busClk => SDAddr[30]~reg0.CLK
busClk => SDAddr[29]~reg0.CLK
busClk => SDAddr[28]~reg0.CLK
busClk => SDAddr[27]~reg0.CLK
busClk => SDAddr[26]~reg0.CLK
busClk => SDAddr[25]~reg0.CLK
busClk => SDAddr[24]~reg0.CLK
busClk => SDAddr[23]~reg0.CLK
busClk => SDAddr[22]~reg0.CLK
busClk => SDAddr[21]~reg0.CLK
busClk => SDAddr[20]~reg0.CLK
busClk => SDAddr[19]~reg0.CLK
busClk => SDAddr[18]~reg0.CLK
busClk => SDAddr[17]~reg0.CLK
busClk => SDAddr[16]~reg0.CLK
busClk => SDAddr[15]~reg0.CLK
busClk => SDAddr[14]~reg0.CLK
busClk => SDAddr[13]~reg0.CLK
busClk => SDAddr[12]~reg0.CLK
busClk => SDAddr[11]~reg0.CLK
busClk => SDAddr[10]~reg0.CLK
busClk => SDAddr[9]~reg0.CLK
busClk => SDAddr[8]~reg0.CLK
busClk => SDAddr[7]~reg0.CLK
busClk => SDAddr[6]~reg0.CLK
busClk => SDAddr[5]~reg0.CLK
busClk => SDAddr[4]~reg0.CLK
busClk => SDAddr[3]~reg0.CLK
busClk => SDAddr[2]~reg0.CLK
busClk => SDAddr[1]~reg0.CLK
busClk => SDAddr[0]~reg0.CLK
busClk => rstShift[5].CLK
busClk => rstShift[4].CLK
busClk => rstShift[3].CLK
busClk => rstShift[2].CLK
busClk => rstShift[1].CLK
busClk => rstShift[0].CLK
busClk => spiTransCtrlShift[5].CLK
busClk => spiTransCtrlShift[4].CLK
busClk => spiTransCtrlShift[3].CLK
busClk => spiTransCtrlShift[2].CLK
busClk => spiTransCtrlShift[1].CLK
busClk => spiTransCtrlShift[0].CLK
busClk => spiTransStatusSTB.CLK
busClk => spiTransStatusReg1.CLK
busClk => spiTransStatusReg2.CLK
busClk => spiTransStatusReg3.CLK
busClk => spiDirectAccessRxDataSTB[7].CLK
busClk => spiDirectAccessRxDataSTB[6].CLK
busClk => spiDirectAccessRxDataSTB[5].CLK
busClk => spiDirectAccessRxDataSTB[4].CLK
busClk => spiDirectAccessRxDataSTB[3].CLK
busClk => spiDirectAccessRxDataSTB[2].CLK
busClk => spiDirectAccessRxDataSTB[1].CLK
busClk => spiDirectAccessRxDataSTB[0].CLK
busClk => SDWriteErrorSTB[1].CLK
busClk => SDWriteErrorSTB[0].CLK
busClk => SDReadErrorSTB[1].CLK
busClk => SDReadErrorSTB[0].CLK
busClk => SDInitErrorSTB[1].CLK
busClk => SDInitErrorSTB[0].CLK
rstFromWire => always2~0.IN1
dataIn[0] => spiTransTypeSTB~1.DATAB
dataIn[0] => spiDirectAccessTxDataSTB~7.DATAB
dataIn[0] => SDAddr~31.DATAB
dataIn[0] => SDAddr~23.DATAB
dataIn[0] => SDAddr~15.DATAB
dataIn[0] => SDAddr~7.DATAB
dataIn[0] => spiClkDelay~7.DATAB
dataIn[0] => always0~3.IN0
dataIn[0] => always0~1.IN0
dataIn[1] => spiTransTypeSTB~0.DATAB
dataIn[1] => spiDirectAccessTxDataSTB~6.DATAB
dataIn[1] => SDAddr~30.DATAB
dataIn[1] => SDAddr~22.DATAB
dataIn[1] => SDAddr~14.DATAB
dataIn[1] => SDAddr~6.DATAB
dataIn[1] => spiClkDelay~6.DATAB
dataIn[2] => spiDirectAccessTxDataSTB~5.DATAB
dataIn[2] => SDAddr~29.DATAB
dataIn[2] => SDAddr~21.DATAB
dataIn[2] => SDAddr~13.DATAB
dataIn[2] => SDAddr~5.DATAB
dataIn[2] => spiClkDelay~5.DATAB
dataIn[3] => spiDirectAccessTxDataSTB~4.DATAB
dataIn[3] => SDAddr~28.DATAB
dataIn[3] => SDAddr~20.DATAB
dataIn[3] => SDAddr~12.DATAB
dataIn[3] => SDAddr~4.DATAB
dataIn[3] => spiClkDelay~4.DATAB
dataIn[4] => spiDirectAccessTxDataSTB~3.DATAB
dataIn[4] => SDAddr~27.DATAB
dataIn[4] => SDAddr~19.DATAB
dataIn[4] => SDAddr~11.DATAB
dataIn[4] => SDAddr~3.DATAB
dataIn[4] => spiClkDelay~3.DATAB
dataIn[5] => spiDirectAccessTxDataSTB~2.DATAB
dataIn[5] => SDAddr~26.DATAB
dataIn[5] => SDAddr~18.DATAB
dataIn[5] => SDAddr~10.DATAB
dataIn[5] => SDAddr~2.DATAB
dataIn[5] => spiClkDelay~2.DATAB
dataIn[6] => spiDirectAccessTxDataSTB~1.DATAB
dataIn[6] => SDAddr~25.DATAB
dataIn[6] => SDAddr~17.DATAB
dataIn[6] => SDAddr~9.DATAB
dataIn[6] => SDAddr~1.DATAB
dataIn[6] => spiClkDelay~1.DATAB
dataIn[7] => spiDirectAccessTxDataSTB~0.DATAB
dataIn[7] => SDAddr~24.DATAB
dataIn[7] => SDAddr~16.DATAB
dataIn[7] => SDAddr~8.DATAB
dataIn[7] => SDAddr~0.DATAB
dataIn[7] => spiClkDelay~0.DATAB
dataOut[0] <= Selector7.DB_MAX_OUTPUT_PORT_TYPE
dataOut[1] <= Selector6.DB_MAX_OUTPUT_PORT_TYPE
dataOut[2] <= Selector5.DB_MAX_OUTPUT_PORT_TYPE
dataOut[3] <= Selector4.DB_MAX_OUTPUT_PORT_TYPE
dataOut[4] <= Selector3.DB_MAX_OUTPUT_PORT_TYPE
dataOut[5] <= Selector2.DB_MAX_OUTPUT_PORT_TYPE
dataOut[6] <= Selector1.DB_MAX_OUTPUT_PORT_TYPE