cntr_umi.tdf

FPGA直接读取SD卡扇区数据

--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" lpm_modulus=1 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=1 clk_en clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 8.0SP1 cbx_cycloneii 2008:06:02:292401 cbx_lpm_add_sub 2008:06:02:292401 cbx_lpm_compare 2008:06:02:292401 cbx_lpm_counter 2008:06:02:292401 cbx_lpm_decode 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratix 2008:06:02:292401 cbx_stratixii 2008:06:02:292401  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( cin0_used, cin1_used, cin_used, lut_mask, operation_mode, output_mode, power_up, register_cascade_mode, sum_lutc_input, synch_mode, x_on_violation)
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 3 
SUBDESIGN cntr_umi
( 
	clk_en	:	input;
	clock	:	input;
	q[0..0]	:	output;
	sclr	:	input;
) 
VARIABLE
	cmpr1_aeb_int	:	WIRE;
	cmpr1_aeb	:	WIRE;
	cmpr1_dataa[0..0]	:	WIRE;
	cmpr1_datab[0..0]	:	WIRE;
	counter_cella0 : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "11AA",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	cout_bit : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "F8F8",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "off"
		);
	aclr	: NODE;
	aclr_actual	: WIRE;
	compare_result	: WIRE;
	data[0..0]	: NODE;
	modulus_bus[0..0]	: WIRE;
	modulus_trigger	: WIRE;
	safe_q[0..0]	: WIRE;
	sload	: NODE;
	time_to_clear	: WIRE;
	updownDir	: WIRE;

BEGIN 
	IF ((0,cmpr1_dataa[]) == (0,cmpr1_datab[])) THEN
		cmpr1_aeb_int = VCC;
	ELSE
		cmpr1_aeb_int = GND;
	END IF;
	cmpr1_aeb = cmpr1_aeb_int;
	cmpr1_dataa[] = safe_q[];
	cmpr1_datab[] = modulus_bus[];
	counter_cella[0..0].aclr = aclr_actual;
	counter_cella[0..0].aload = B"0";
	counter_cella[0..0].clk = clock;
	counter_cella[0..0].dataa = safe_q[];
	counter_cella[0..0].datab = B"0";
	counter_cella[0..0].datac = ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updownDir)));
	counter_cella[0..0].ena = clk_en;
	counter_cella[0..0].sclr = sclr;
	counter_cella[0..0].sload = (sload # modulus_trigger);
	cout_bit.cin = counter_cella[0].cout;
	cout_bit.dataa = updownDir;
	cout_bit.datab = time_to_clear;
	aclr = GND;
	aclr_actual = aclr;
	compare_result = cmpr1_aeb;
	data[] = GND;
	modulus_bus[] = B"0";
	modulus_trigger = cout_bit.combout;
	q[] = safe_q[];
	safe_q[] = counter_cella[0..0].regout;
	sload = GND;
	time_to_clear = compare_result;
	updownDir = B"1";
END;
--VALID FILE