top.sta.rpt

来自「FPGA直接读取SD卡扇区数据」· RPT 代码 · 共 447 行 · 第 1/5 页

; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[21]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[22]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[23]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[24]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[25]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[26]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[27]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[28]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[29]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[30]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[31]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[0]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[10]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[11]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[12]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[13]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[14]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[15]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[16]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[17]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[18]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[19]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[1]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[20]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[21]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[22]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[23]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[24]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[25]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[26]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[27]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[28]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[29]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[2]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[30]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[31]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[3]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[4]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[5]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[6]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[7]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[8]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[9]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[0]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[0]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[10]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[10]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[11]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[11]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[12]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[12]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[13]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[13]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[14]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[14]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[15]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[15]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[16]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[16]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[17]              ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[17]~_Duplicate_1 ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[1]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[1]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[2]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[2]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[3]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[3]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[4]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[4]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[5]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[5]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[6]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[6]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[7]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[7]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[8]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[8]~_Duplicate_1  ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[9]               ;
; 11.553 ; 11.435       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[9]~_Duplicate_1  ;
+--------+--------------+----------------+-------+-----------------+--------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                            ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                          ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------+
; eth_md_io       ; clk0       ; 5.939  ; 6.104  ; Rise       ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ;
; flash_miso_i    ; clk0       ; 2.835  ; 3.069  ; Rise       ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ;
; int_i           ; clk0       ; 12.256 ; 12.800 ; Rise       ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ;