readwritesdblock.v

FPGA直接读取SD卡扇区数据

      begin
        NextState_rwBlkSt <= `WR_BUSY_DEL2;
      end
    end
    `WR_BUSY_SEND_CMD1:
    begin
      next_txDataOut <= 8'hff;
      next_txDataWen <= 1'b1;
      next_rxDataRdyClr <= 1'b1;
      next_delCnt1 <= 8'h00;
      NextState_rwBlkSt <= `WR_BUSY_DEL1;
    end
    `WR_BUSY_DEL2:
    begin
      next_delCnt2 <= delCnt2 + 1'b1;
      if (delCnt2 == 8'hff)
      begin
        NextState_rwBlkSt <= `WR_BUSY_DEL1;
      end
    end
    `WR_BUSY_INIT_LOOP:
    begin
      next_timeOutCnt <= 12'h000;
      NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1;
    end
    `RD_CMD_SEND_CMD:
    begin
      next_cmdByte <= 8'h51;
      //CMD17 Block Read
      next_dataByte1 <= blockAddr[31:24];
      next_dataByte2 <= blockAddr[23:16];
      next_dataByte3 <= blockAddr[15:8];
      next_dataByte4 <= blockAddr[7:0];
      next_checkSumByte <= 8'hff;
      next_sendCmdReq <= 1'b1;
      NextState_rwBlkSt <= `RD_CMD_DEL;
    end
    `RD_CMD_WT_FIN:
    begin
      if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00))
      begin
        NextState_rwBlkSt <= `WT_REQ;
        next_readError <= `READ_CMD_ERROR;
      end
      else if (sendCmdRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_INIT_LOOP;
      end
    end
    `RD_CMD_DEL:
    begin
      next_sendCmdReq <= 1'b0;
      NextState_rwBlkSt <= `RD_CMD_WT_FIN;
    end
    `RD_TOKEN_CHK_LOOP:
    begin
      if (locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_DEL2;
        next_timeOutCnt <= timeOutCnt + 1'b1;
        next_delCnt1 <= 8'h00;
      end
      else if (timeOutCnt == `ONE_HUNDRED_MS)
      begin
        NextState_rwBlkSt <= `WT_REQ;
        next_readError <= `READ_TOKEN_ERROR;
      end
      else
      begin
        NextState_rwBlkSt <= `RD_DATA_CLR_RX;
        next_rxDataRdyClr <= 1'b1;
      end
    end
    `RD_TOKEN_WT_FIN:
    begin
      if (rxDataRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_CHK_LOOP;
        next_locRespByte <= rxDataIn;
      end
    end
    `RD_TOKEN_SEND_CMD:
    begin
      next_txDataOut <= 8'hff;
      next_txDataWen <= 1'b1;
      next_rxDataRdyClr <= 1'b1;
      NextState_rwBlkSt <= `RD_TOKEN_DEL1;
    end
    `RD_TOKEN_DEL2:
    begin
      next_delCnt1 <= delCnt1 + 1'b1;
      next_delCnt2 <= 8'h00;
      if (delCnt1 == `MAX_8_BIT)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD;
      end
      else
      begin
        NextState_rwBlkSt <= `RD_TOKEN_DEL3;
      end
    end
    `RD_TOKEN_INIT_LOOP:
    begin
      next_timeOutCnt <= 12'h000;
      NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD;
    end
    `RD_TOKEN_DEL1:
    begin
      next_txDataWen <= 1'b0;
      next_rxDataRdyClr <= 1'b0;
      NextState_rwBlkSt <= `RD_TOKEN_WT_FIN;
    end
    `RD_TOKEN_DEL3:
    begin
      next_delCnt2 <= delCnt2 + 1'b1;
      if (delCnt2 == 8'hff)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_DEL2;
      end
    end
    `RD_DATA_ST_LOOP:
    begin
      next_txDataWen <= 1'b1;
      next_txDataOut <= 8'hff;
      next_loopCnt <= loopCnt + 1'b1;
      NextState_rwBlkSt <= `RD_DATA_WT_DATA;
    end
    `RD_DATA_WT_DATA:
    begin
      next_txDataWen <= 1'b0;
      if (rxDataRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `RD_DATA_CHK_LOOP;
        next_rxFifoWen <= 1'b1;
        next_rxDataRdyClr <= 1'b1;
        next_rxFifoData <= rxDataIn;
      end
    end
    `RD_DATA_CHK_LOOP:
    begin
      if (loopCnt == 9'b000000000)
      begin
        NextState_rwBlkSt <= `RD_DATA_CS_ST1;
        next_rxDataRdyClr <= 1'b0;
        next_rxFifoWen <= 1'b0;
      end
      else
      begin
        NextState_rwBlkSt <= `RD_DATA_ST_LOOP;
        next_rxDataRdyClr <= 1'b0;
        next_rxFifoWen <= 1'b0;
      end
    end
    `RD_DATA_CLR_RX:
    begin
      NextState_rwBlkSt <= `RD_DATA_ST_LOOP;
      next_rxDataRdyClr <= 1'b0;
      next_loopCnt <= 9'b000000000;
    end
    `RD_DATA_CS_FIN2:
    begin
      next_txDataWen <= 1'b0;
      if (txDataEmpty == 1'b1)
      begin
        NextState_rwBlkSt <= `WT_REQ;
      end
    end
    `RD_DATA_CS_FIN1:
    begin
      next_txDataWen <= 1'b0;
      NextState_rwBlkSt <= `RD_DATA_CS_ST2;
    end
    `RD_DATA_CS_ST1:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `RD_DATA_CS_FIN1;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `RD_DATA_CS_ST2:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `RD_DATA_CS_FIN2;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_DATA_D_FIN:
    begin
      next_txDataWen <= 1'b0;
      if (loopCnt == 9'b000000000)
      begin
        NextState_rwBlkSt <= `WR_DATA_CS_ST1;
      end
      else
      begin
        NextState_rwBlkSt <= `WR_DATA_RD_FIFO1;
      end
    end
    `WR_DATA_D_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_DATA_D_FIN;
        next_txDataOut <= txFifoData;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_DATA_RD_FIFO1:
    begin
      next_txFifoRen <= 1'b1;
      next_loopCnt <= loopCnt + 1'b1;
      NextState_rwBlkSt <= `WR_DATA_RD_FIFO2;
    end
    `WR_DATA_RD_FIFO2:
    begin
      next_txFifoRen <= 1'b0;
      NextState_rwBlkSt <= `WR_DATA_D_ST;
    end
    `WR_DATA_LOOP_INIT:
    begin
      next_loopCnt <= 9'b000000000;
      NextState_rwBlkSt <= `WR_DATA_RD_FIFO1;
    end
    `WR_DATA_CS_ST1:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_DATA_CS_FIN1;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_DATA_CS_FIN1:
    begin
      next_txDataWen <= 1'b0;
      NextState_rwBlkSt <= `WR_DATA_CS_ST2;
    end
    `WR_DATA_CS_FIN2:
    begin
      next_txDataWen <= 1'b0;
      next_timeOutCnt <= 12'h000;
      if (txDataEmpty == 1'b1)
      begin
        NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST;
      end
    end
    `WR_DATA_CS_ST2:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_DATA_CS_FIN2;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_DATA_CHK_RESP:
    begin
      if (timeOutCnt == `WR_RESP_TOUT)
      begin
        NextState_rwBlkSt <= `WT_REQ;
        next_writeError <= `WRITE_DATA_ERROR;
      end
      else if (locRespByte[4:0] == 5'h5)
      begin
        NextState_rwBlkSt <= `WR_BUSY_INIT_LOOP;
      end
      else
      begin
        NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST;
      end
    end
    `WR_DATA_REQ_RESP_ST:
    begin
      NextState_rwBlkSt <= `WR_DATA_DEL;
      next_txDataOut <= 8'hff;
      next_txDataWen <= 1'b1;
      next_timeOutCnt <= timeOutCnt + 1'b1;
      next_rxDataRdyClr <= 1'b1;
    end
    `WR_DATA_REQ_RESP_FIN:
    begin
      if (rxDataRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `WR_DATA_CHK_RESP;
        next_locRespByte <= rxDataIn;
      end
    end
    `WR_DATA_DEL:
    begin
      NextState_rwBlkSt <= `WR_DATA_REQ_RESP_FIN;
      next_txDataWen <= 1'b0;
      next_rxDataRdyClr <= 1'b0;
    end
  endcase
end

// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst == 1'b1)
    CurrState_rwBlkSt <= `ST_RW_SD;
  else
    CurrState_rwBlkSt <= NextState_rwBlkSt;
end

// Registered outputs logic
always @ (posedge clk)
begin
  if (rst == 1'b1)
  begin
    readWriteSDBlockRdy <= 1'b0;
    spiCS_n <= 1'b1;
    readError <= 1'b0;
    writeError <= 1'b0;
    txDataOut <= 8'h00;
    txDataWen <= 1'b0;
    rxDataRdyClr <= 1'b0;
    cmdByte <= 8'h00;
    dataByte1 <= 8'h00;
    dataByte2 <= 8'h00;
    dataByte3 <= 8'h00;
    dataByte4 <= 8'h00;
    checkSumByte <= 8'h00;
    sendCmdReq <= 1'b0;
    txFifoRen <= 1'b0;
    rxFifoWen <= 1'b0;
    rxFifoData <= 8'h00;
    loopCnt <= 8'h00;
    delCnt1 <= 8'h00;
    delCnt2 <= 8'h00;
    timeOutCnt <= 12'h000;
    locRespByte <= 8'h00;
  end
  else 
  begin
    readWriteSDBlockRdy <= next_readWriteSDBlockRdy;
    spiCS_n <= next_spiCS_n;
    readError <= next_readError;
    writeError <= next_writeError;
    txDataOut <= next_txDataOut;
    txDataWen <= next_txDataWen;
    rxDataRdyClr <= next_rxDataRdyClr;
    cmdByte <= next_cmdByte;
    dataByte1 <= next_dataByte1;
    dataByte2 <= next_dataByte2;
    dataByte3 <= next_dataByte3;
    dataByte4 <= next_dataByte4;
    checkSumByte <= next_checkSumByte;
    sendCmdReq <= next_sendCmdReq;
    txFifoRen <= next_txFifoRen;
    rxFifoWen <= next_rxFifoWen;
    rxFifoData <= next_rxFifoData;
    loopCnt <= next_loopCnt;
    delCnt1 <= next_delCnt1;
    delCnt2 <= next_delCnt2;
    timeOutCnt <= next_timeOutCnt;
    locRespByte <= next_locRespByte;
  end
end

endmodule