📄 7102atest.lst
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1 000000 ; FILENAME : 7102ATEST.ASM
2 000000 ; AUTHOR : allan
3 000000 ; REVISION : 2008/06/02 V1.0 First issue
4 000000
5 000000 ;*******************************************************************************
6 000000 ;* (c) Copyright 2004, SONiX TECHNOLOGY CO., LTD.
7 000000 ;*******************************************************************************
8 000000
9 000000 CHIP SN8P2612 ; Select the CHIP
10 000000 //{{SONIX_CODE_OPTION
11 000000 .Code_Option Noise_Filter Enable
12 000000 .Code_Option Reset_Pin P15
13 000000 .Code_Option Watch_Dog Disable ; Disable Watchdog
14 000000 .Code_Option High_Clk IHRC_16M ; Internal 16M RC Oscillator
15 000000 .Code_Option Fcpu #2 ; Fcpu = Fosc/4
16 000000 .Code_Option Security Disable
17 000000 .Code_Option LVD LVD_H ; 2.4V Reset Enable LVD36 bit of PFLAG for 3.6V Low Voltage Indicator
18 000000 //}}SONIX_CODE_OPTION
19 000000
20 000000 ;-------------------------------------------------------------------------------
21 000000 ; Include Files
22 000000 ;-------------------------------------------------------------------------------
23 000000
24 000000 ;-------------------------------------------------------------------------------
25 000000 ; Constants Definition
26 000000 ;-------------------------------------------------------------------------------
27 000000
28 000000 INCLUDE EQU.asm
29 000000 ;*********************************************
30 000000 ;I/O DEFINE
31 000000 ;*********************************************
32 000000
33 E 000000D5 SCS EQU P5.0
34 E 000000C5 SCS_M EQU P5M.0
35 E 000100D5 SCK EQU P5.1
36 E 000100C5 SCK_M EQU P5M.1
37 E 000300D5 IRQ EQU P5.3
38 E 000300C5 IRQ_M EQU P5M.3
39 E 000100D1 SDIO EQU P1.1
40 E 000100C1 SDIO_M EQU P1M.1
41 E 000000D1 CKO EQU P1.0
42 E 000000C1 CKO_M EQU P1M.0
43 E 000600D1 TRS EQU P1.6
44 E 000600C1 TRS_M EQU P1M.6
45 E 000400D1 PWON EQU P1.4
46 E 000400C1 PWON_M EQU P1M.4
47 E 000400D5 TRE EQU P5.4
48 E 000400C5 TRE_M EQU P5M.4
49 000000
50 000000
51 000000
52 000000
53 E 000200D1 LED1 EQU P1.2
54 E 000300D1 LED2 EQU P1.3
55 E 000000D0 KEY1 EQU P0.0
56 E 000500D1 KEY2 EQU P1.5
57 000000
58 000000
59 000000
60 000000
61 E 00000046 kdelaytime EQU 70
62 000000
63 000000 ;*********************************************
64 000000 ;7102A DEFINE
65 000000 ;*********************************************
66 E 00000070 CMD_RFRESET EQU #0X70
67 E 00000000 CMD_CTRLW EQU #0X00
68 E 00000080 CMD_CTRLR EQU #0x80
69 E 00000040 CMD_DATAW EQU #0x40
70 E 000000C0 CMD_DATAR EQU #0xC0
71 E 000000E0 cmd_rfr equ #0xE0
72 000000
73 000000
74 E 00000000 SYSTEMCLOCK_REG EQU #0x00
75 E 00000001 PLL1_REG EQU #0x01
76 E 00000002 PLL2_REG EQU #0x02
77 E 00000003 PLL3_REG EQU #0x03
78 E 00000004 PLL4_REG EQU #0x04
79 E 00000005 CRYSTAL_REG EQU #0x05
80 E 00000006 TX1_REG EQU #0x06
81 E 00000007 TX2_REG EQU #0x07
82 E 00000008 RX1_REG EQU #0x08
83 E 00000009 RX2_REG EQU #0x09
84 E 0000000A ADC_REG EQU #0x0A
85 E 0000000B FIFO_REG EQU #0x0B
86 E 0000000C CODE_REG EQU #0x0C
87 E 0000000D PIN_REG EQU #0x0D
88 E 0000000E CALIBRATION_REG EQU #0x0E
89 E 0000000F MODE_REG EQU #0x0F
90 000000
91 000000
92 000000 /*
93 000000 DATA1 EQU #0XC5
94 000000 DATA2 EQU #0X38
95 000000 DATA3 EQU #0X27
96 000000 DATA4 EQU #0X41
97 000000 */
98 000000
99 000000
100 000000 ;-------------------------------------------------------------------------------
101 000000 ; Variables Definition
102 000000 ;-------------------------------------------------------------------------------
103 000000 .DATA
104 000000 org 0h ;Data section start from RAM address 0
105 000000 INCLUDE RAM.asm
106 000000 ORG 000H
107 000000
108 0000 D TIME_250US DS 1
109 0001 D TIME_MS DS 1
110 0002 D TEMP_WRITE DS 1
111 0003 D TEMP_READ DS 1
112 0004 D TEMP_ID1 DS 1
113 0005 D TEMP_ID2 DS 1
114 0006 D TEMP_ID3 DS 1
115 0007 D TEMP_ID4 DS 1
116 0008 D TEMP_CAL1_L DS 1
117 0009 D TEMP_CAL1_M DS 1
118 000A D TEMP_CAL2_L DS 1
119 000B D TEMP_CAL2_M DS 1
120 000C D Bt_Cont DS 1
121 000D D address ds 1
122 000E D DATA_M DS 1
123 000F D DATA_L DS 1
124 000010
125 000010
126 000010
127 0010 D keychat DS 1
128 0011 D keyinbuf1 DS 1
129 0012 D keychkbuf1 DS 1
130 0013 D keyoldbuf1 DS 1
131 0014 D keycvtbuf1 DS 1
132 000015
133 000015
134 000015
135 000015
136 000015
137 000015
138 0015 D key1_counter ds 1
139 0016 D key2_counter ds 1
140 000017
141 000017
142 000017
143 000017
144 000017
145 000017
146 000017
147 000017
148 000017
149 000017
150 0017 D DATA1 DS 1
151 0018 D DATA2 DS 1
152 0019 D DATA3 DS 1
153 001A D DATA4 DS 1
154 001B D datax DS 1
155 00001C
156 00001C
157 001C D t_counter ds 1
158 00001D
159 001D D T_PWM_H DS 1
160 001E D T_PWM_L DS 1
161 001F D pwm_counter ds 1
162 0020 D ack_counter ds 1
163 0021 D counter_rx DS 1
164 000022
165 0022 D FLAG DS 1
166 E 00000022 f_1ms EQU FLAG.0
167 E 00010022 f_100Us EQU FLAG.1
168 E 00020022 F_KEY_2 EQU FLAG.2
169 E 00030022 fkey_in EQU FLAG.3
170 E 00040022 F_KEY_1 EQU FLAG.4
171 E 00050022 F_KEY2 EQU FLAG.5
172 E 00060022 f_s_ok EQU FLAG.6
173 E 00070022 f_m_ok EQU FLAG.7
174 000023
175 0023 D FLAG1 DS 1
176 E 00000023 f_rx_ok EQU FLAG1.0
177 E 00010023 f_ack equ FLAG1.1
178 000024 ;-------------------------------------------------------------------------------
179 000024 ; Bit Variables Definition
180 000024 ;-------------------------------------------------------------------------------
181 000024
182 000024 ; Wk00B0 EQU Wk00.0 ;Bit 0 of Wk00
183 000024 ; Iwk00B1 EQU Iwk00.1 ;Bit 1 of Iwk00
184 000024
185 000024 ;-------------------------------------------------------------------------------
186 000024 ; Code section
187 000024 ;-------------------------------------------------------------------------------
188 000000 .CODE
189 000000
190 000000 ORG 0 ;Code section start
191 000000 804E(2) jmp Reset ;Reset vector
192 000001 ;Address 4 to 7 are reserved
193 000008 ORG 8
194 000008 8009(2) jmp Isr ;Interrupt vector
195 000009
196 000009
197 000009 INCLUDE ISR.asm
198 000009 ISR:
199 000009 0400(1) PUSH
200 00000A
201 00000A ;-----------------------------------
202 00000A ; check which interrupt happen
203 00000A ;-----------------------------------
204 00000A int0chk:
205 00000A 7CC8(1+S) b0bts1 ft0irq
206 00000B 800D(2) jmp intc0chk
207 00000C 8010(2) jmp int0
208 00000D
209 00000D
210 00000D intc0chk:
211 00000D
212 00000D 7DC8(1+S) b0bts1 ftc0irq
213 00000E 804C(2) jmp int_exit
214 00000F 8037(2) jmp intC0
215 000010
216 000010 int0:
217 000010 64C8(1) b0bclr ft0irq
218 000011 2DF0(1) MOV A,#0xf0 ;reload to T0C
219 000012 2FD9(1) B0MOV T0C,A
220 000013 6822(1) b0bset f_1ms
221 000014 2621(1+S) DECMS counter_rx
222 000015 8018(2) JMP $+3
223 000016 ; MOV A,#50
224 000016 ; MOV counter_rx,A
225 000016 0000(1) NOP
226 000017 0000(1) NOP
227 000018 keycheck0:
228 000018 78D0(1+S) b0bts1 key1
229 000019 801C(2) jmp $+3
230 00001A 2B15(1) clr key1_counter
231 00001B 801D(2) jmp $+2
232 00001C 1615(1+S) incms key1_counter
233 00001D
234 00001D 7DD1(1+S) b0bts1 key2
235 00001E 8021(2) jmp $+3
236 00001F 2B16(1) clr key2_counter
237 000020 8022(2) jmp $+2
238 000021 1616(1+S) incms key2_counter
239 000022
240 000022
241 000022
242 000022 1E16(1) mov a,key2_counter
243 000023 1D28(1) xor a,#40
244 000024 7886(1+S) b0bts1 fz
245 000025 8027(2) jmp $+2
246 000026 6A22(1) b0bset f_key_2
247 000027 1E16(1) mov a,key2_counter
248 000028 24FA(1) SUB a,#250
249 000029 7886(1+S) b0bts1 fz
250 00002A 802C(2) JMP $+2
251 00002B 2B16(1) clr key2_counter
252 00002C
253 00002C
254 00002C 1E15(1) mov a,key1_counter
255 00002D 1D28(1) xor a,#40
256 00002E 7886(1+S) b0bts1 fz
257 00002F 8031(2) jmp $+2
258 000030 6C22(1) b0bset f_key_1
259 000031 1E15(1) mov a,key1_counter
260 000032 24FA(1) SUB a,#250
261 000033 7886(1+S) b0bts1 fz
262 000034 8036(2) JMP $+2
263 000035 2B15(1) clr key1_counter
264 000036
265 000036 804C(2) jmp int_exit
266 000037
267 000037
268 000037
269 000037
270 000037
271 000037
272 000037 /*
273 000037 ;============================================
274 000037 ; do key debounce
275 000037 ;============================================
276 000037 dkeychat:
277 000037 b0mov a,keychat
278 000037 b0bts0 fz ;is keychat <> 0
279 000037 jmp dkeychat90 ;is A = 0
280 000037 decms keychat ;keychat1 --
281 000037 jmp dkeychat90
282 000037 dkeychat90:
283 000037 jmp int_exit
284 000037
285 000037
286 000037 */
287 000037
288 000037 intc0:
289 000037 65C8(1) b0bclr ftc0irq
290 000038 2DF0(1) mov a,#0F0H
291 000039 1FDB(1) mov tc0c,a
292 00003A 6922(1) B0BSET F_100US
293 00003B
294 00003B 7D22(1+S) b0bts1 f_key2
295 00003C 804B(2) jmp intc0_20
296 00003D 803E(2) jmp intc0_10
297 00003E intc0_10:
298 00003E 161D(1+S) INCMS T_PWM_H
299 00003F 161E(1+S) INCMS T_PWM_L
300 000040 1E1D(1) MOV A,T_PWM_H
301 000041 1B1B(1) XOR A,datax
302 000042 7886(1+S) B0BTS1 FZ
303 000043 8046(2) JMP $+3
304 000044 ; B0BCLR LED2
305 000044 ; b0bclr led1
306 000044
307 000044 1E1E(1) MOV A,T_PWM_L
308 000045 1D14(1) XOR A,#20
309 000046 7886(1+S) B0BTS1 FZ
310 000047 804C(2) JMP $+5
311 000048 ; B0BSET LED2
312 000048 ; b0bset led1
313 000048
314 000048 2B1D(1) CLR T_PWM_H
315 000049 2B1E(1) CLR T_PWM_L
316 00004A 804B(2) JMP intc0_90
317 00004B
318 00004B intc0_20:
319 00004B /*
320 00004B INCMS T_PWM_H
321 00004B INCMS T_PWM_L
322 00004B MOV A,T_PWM_H
323 00004B XOR A,data1
324 00004B B0BTS1 FZ
325 00004B JMP $+2
326 00004B B0BCLR LED1
327 00004B
328 00004B MOV A,T_PWM_L
329 00004B XOR A,#20
330 00004B B0BTS1 FZ
331 00004B JMP $+4
332 00004B B0BSET LED1
333 00004B CLR T_PWM_H
334 00004B CLR T_PWM_L
335 00004B JMP intc0_90
336 00004B
337 00004B */
338 00004B intc0_90:
339 00004B 804C(2) jmp int_exit
340 00004C
341 00004C
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