fir_r8.asm

davinci技术 源码 视频监控汇编源码

        SPMASK
||^     ZERO    .L2     B_sum1:B_sum0
||^     ZERO    .L1     A_sum5:A_sum4
||^     SHRU    .S2     B_i,        3,          B_i
||^     STDW    .D2T1   A13:A12,    *+B_SP[1]

        SPMASK
||^     ZERO    .L2     B_sum3:B_sum2
||^     ZERO    .L1     A_sum7:A_sum6
||^     SUB     .S2     B_i,        1,          B_i
||^     STDW    .D2T2   B11:B10,    *+B_SP[5]

        SPMASK
||      DDOTPL2 .M1     A_d3d2:A_d1d0, A_c1c0,  A_s1a:A_s0a     ;[ 8,1]
||      DDOTPL2 .M2     B_d7d6:B_d5d4, B_c5c4,  B_s1c:B_s0c     ;[ 8,1]
||^     STDW    .D2T2   B13:B12,    *+B_SP[4]

*- Stage 1 -----------------------------------------------------------------*
        DMV     .S1X    A_d9d8,     B_d7d6,     A_d9d8_:A_d7d6_ ;[ 9,1]
||      DMV     .S2X    B_d5d4,     A_d3d2,     B_d5d4_:B_d3d2_ ;[ 9,1]
||      DDOTPL2 .M1     A_dbda:A_d9d8, A_c3c2,  A_s7b:A_s6b     ;[ 9,1]
||      DDOTPL2 .M2     B_dfde:B_dddc, B_c7c6,  B_s7d:B_s6d     ;[ 9,1]

        DMV     .S2X    B_dddc,     A_dbda,     B_dddc_:B_dbda_ ;[10,1]
||      DDOTPL2 .M2     B_d5d4_:B_d3d2_, B_c3c2,B_s1b:B_s0b     ;[10,1]
||      DDOTPL2 .M1     A_dbda:A_d9d8, A_c7c6,  A_s3d:A_s2d     ;[10,1]

        DDOTPL2 .M1     A_d9d8_:A_d7d6_, A_c5c4,A_s3c:A_s2c     ;[11,1]
||      DDOTPL2 .M2     B_dddc_:B_dbda_, B_c5c4,B_s7c:B_s6c     ;[11,1]

        DDOTPL2 .M2     B_dddc_:B_dbda_, B_c7c6,B_s5d:B_s4d     ;[12,1]
||      DDOTPL2 .M1     A_d9d8_:A_d7d6_, A_c1c0,A_s7a:A_s6a     ;[12,1]

        DDOTPL2 .M2     B_d7d6:B_d5d4, B_c1c0,  B_s5a:B_s4a     ;[13,1]
||      DDOTPL2 .M1     A_d9d8_:A_d7d6_, A_c3c2,A_s5b:A_s4b     ;[13,1]

        ADD     .L2     B_s1b,      B_s1c,      B_s1bc          ;[14,1]
||      DDOTPL2 .M1     A_d9d8_:A_d7d6_, A_c7c6,A_s1d:A_s0d     ;[14,1]
||      DDOTPL2 .M2     B_d7d6:B_d5d4, B_c3c2,  B_s3b:B_s2b     ;[14,1]

        ADD     .S2     B_s0b,      B_s0c,      B_s0bc          ;[15,1]
||      ADD     .D1     A_s3c,      A_s3d,      A_s3cd          ;[15,1]
||      ADD     .L1     A_s2c,      A_s2d,      A_s2cd          ;[15,1]
||      DDOTPL2 .M2     B_d5d4_:B_d3d2_, B_c1c0,B_s3a:B_s2a     ;[15,1]
||      DDOTPL2 .M1     A_dbda:A_d9d8, A_c5c4,  A_s5c:A_s4c     ;[15,1]

        ADD     .D2     B_s7c,      B_s7d,      B_s7cd          ;[16,1]
||      ADD     .L2     B_s6c,      B_s6d,      B_s6cd          ;[16,1]
||      ADD     .D1     A_s6a,      A_s6b,      A_s6ab          ;[16,1]

*- Stage 2 -----------------------------------------------------------------*
        ADD     .D2     B_s5a,      B_s5d,      B_s5ad          ;[17,1]
||      ADD     .L1     A_s7a,      A_s7b,      A_s7ab          ;[17,1]

        ADD     .L2     B_s4a,      B_s4d,      B_s4ad          ;[18,1]
||      ADD     .L1X    A_s7ab,     B_s7cd,     A_s7abcd        ;[18,1]

        ADD     .D1     A_s1a,      A_s1d,      A_s1ad          ;[19,1]
||      ADD     .S1     A_s0a,      A_s0d,      A_s0ad          ;[19,1]
||      ADD     .L2     B_s3a,      B_s3b,      B_s3ab          ;[19,1]
||      ADD     .S2     B_s2a,      B_s2b,      B_s2ab          ;[19,1]
||      ADD     .L1     A_s5b,      A_s5c,      A_s5bc          ;[19,1]

        ADD     .L2X    B_s2ab,     A_s2cd,     B_s2abcd        ;[20,1]
||      ADD     .S1     A_s4b,      A_s4c,      A_s4bc          ;[20,1]
||      ADD     .L1X    A_s6ab,     B_s6cd,     A_s6abcd        ;[20,1]

        ADD     .L2X    B_s0bc,     A_s0ad,     B_s0abcd        ;[21,1]
||      ADD     .S2     B_s2abcd,   B_sum2,     B_sum2          ;[21,1]
||      ADD     .S1X    A_s5bc,     B_s5ad,     A_s5abcd        ;[21,1]

        ADD     .S2X    B_s1bc,     A_s1ad,     B_s1abcd        ;[22,1]
||      ADD     .S1     A_s5abcd,   A_sum5,     A_sum5          ;[22,1]
||      ADD     .D1X    A_s4bc,     B_s4ad,     A_s4abcd        ;[22,1]
||      ADD     .L1     A_s7abcd,   A_sum7,     A_sum7          ;[22,1]

        ADD     .L2     B_s0abcd,   B_sum0,     B_sum0          ;[23,1]
||      ADD     .D2X    B_s3ab,     A_s3cd,     B_s3abcd        ;[23,1]

        ADD     .S2     B_s1abcd,   B_sum1,     B_sum1          ;[24,1]
||      ADD     .L1     A_s4abcd,   A_sum4,     A_sum4          ;[24,1]
||      ADD     .S1     A_s6abcd,   A_sum6,     A_sum6          ;[24,1]

*- Stage 3 -----------------------------------------------------------------*
        ADD     .L2     B_s3abcd,   B_sum3,     B_sum3          ;[25,1]

        NOP             6

        SPKERNELR

OUTER_LOOP:
;;;     EP0, PR0
;;;============================================================================
; cycle 0:
        SPMASK
||^     LDDW    .D1T1   *--A_X_addr[A_TI], A_d3d2:A_d1d0        ;[ 1,1]
; cycle 1: S1
        SPMASK
||^     LDDW    .D2T2   *--B_COEFaddr[B_TC], B_c7c6:B_c5c4      ;[ 2,1]
||^     LDDW    .D1T1   *--A_COEFaddr[A_TC], A_c3c2:A_c1c0      ;[ 2,1]
; cycle 2:
        SPMASK
||^     LDDW    .D2T2   *--B_X_addr[B_TI], B_d7d6:B_d5d4        ;[ 3,1]
; cycle 3: S2
  [B_i] SUB     .S2     B_i,        1,          B_i
        NOP             4
; cycle 4: L1
;        NOP
; cycle 5: D2
;        NOP
; cycle 6: S1 (D1)
;        NOP
; cycle 7:
;        NOP

;;;     EP1, PR1
;;;============================================================================
; cycle 0:
        NOP             9
; cycle 1: S1
;        NOP
; cycle 2:
;        NOP
; cycle 3: S2
;        NOP
; cycle 4: L1
;        NOP
; cycle 5: D2
; B_sum2 ready for use
;        NOP
; cycle 6: S1 (D1)
; A_sum5, A_sum7 ready for use
;        NOP
; cycle 7:
; B_sum0 ready for use
;        NOP

;;;     EP2, PR2
;;;============================================================================
; cycle 0:
; B_sum1, A_sum4, A_sum6 ready for use
;        NOP
; cycle 1: S1
; B_sum3 ready for use
        RPACK2  .S1     A_sum7,     A_sum6,     A_sum76
; cycle 2:
        NOP
; cycle 3: S2
        RPACK2  .S2     B_sum3,     B_sum2,     B_sum32
; cycle 4: L1
        SPMASK
||^     RPACK2  .S1     A_sum5,     A_sum4,     A_sum54
||      ADD     .L1X    A_s5bc,     B_s5ad,     A_s5abcd        ;[21,1]
||^     ADD     .S2     B_s2abcd,   0,          B_sum2          ;[21,1]
; cycle 5: D2
        SPMASK
||^     RPACK2  .S2     B_sum1,     B_sum0,     B_sum10
||      ADD     .D2X    B_s1bc,     A_s1ad,     B_s1abcd        ;[22,1]
||^     ADD     .S1     A_s5abcd,   0,          A_sum5          ;[22,1]
||^     ADD     .L1     A_s7abcd,   0,          A_sum7          ;[22,1]
; cycle 6: S1 (D1)
        SPMASK
||^     STDW    .D1T2   B_sum32:B_sum10, *A_R_addr++
||      ADD     .S1     A_s3c,      A_s3d,      A_s3cd          ;[15,1]
||^     ADD     .L2     B_s0abcd,   0,          B_sum0          ;[23,1]

; cycle 7:
        SPMASK
||^     ADD     .S2     B_s1abcd,   0,          B_sum1          ;[24,1]
||^     ADD     .L1     A_s4abcd,   0,          A_sum4          ;[24,1]
||^     ADD     .S1     A_s6abcd,   0,          A_sum6          ;[24,1]


;;;     KRN
;;;============================================================================
; cycle 0:
        SPMASK
||^     ADD     .L2     B_s3abcd,   0,          B_sum3          ;[25,1]
; cycle 1: S1
  [B_i] B       .S1     OUTER_LOOP
; cycle 2:
        NOP
; cycle 3: S2
        NOP
; cycle 4: L1
        NOP
; cycle 5: D2
        NOP
; cycle 6: S1 (D1)
        SPMASK
||^     STDW    .D1T1   A_sum76:A_sum54, *A_R_addr++
||      ADD     .S1     A_s3c,      A_s3d,      A_s3cd          ;[15,1]
; cycle 7:
        NOP


;; Below will be executed as soon as the epilog of the last iteration begins.
; EP 0
        NOP             8

; EP 1
        SPMASK
||^     LDW     .D2T2   *+B_SP[6*2], B3
||      ADD     .S2     B_s5a,      B_s5d,      B_s5ad          ;[17,1]

        LDDW    .D2T1   *+B_SP[2],  A15:A14

        LDDW    .D2T2   *+B_SP[5],  B11:B10

        LDDW    .D2T2   *+B_SP[4],  B13:B12

        LDDW    .D2T1   *+B_SP[1],  A13:A12

        SPMASK
||      LDW     .D2T2   *+B_SP[3*2], B14
||      ADD     .L2X    B_s1bc,     A_s1ad,     B_s1abcd        ;[22,1]
||^     RET     .S2     B_ret

        SPMASK
||^     LDDW    .D2T1   *B_SP++[10], A11:A10
||      ADD     .S2X    B_s3ab,     A_s3cd,     B_s3abcd        ;[23,1]

        NOP

; EP 2
        RPACK2  .S1     A_sum5,     A_sum4,     A_sum54
||      RPACK2  .S2     B_sum1,     B_sum0,     B_sum10
||      MV      .D2     A_R_addr,   B_R_addr

        RPACK2  .S1     A_sum7,     A_sum6,     A_sum76
||      RPACK2  .S2     B_sum3,     B_sum2,     B_sum32

        STDW    .D2T2   B_sum32:B_sum10, *B_R_addr
||      STDW    .D1T1   A_sum76:A_sum54, *+A_R_addr[1]


        .end


* ======================================================================== *
*  End of file: fir_r8.asm                                                 *
* ------------------------------------------------------------------------ *
*          Copyright (C) 2005 Texas Instruments, Incorporated.             *
*                          All Rights Reserved.                            *
* ======================================================================== *