convenc3.asm

davinci技术 源码 视频监控汇编源码

* ========================================================================  *
*  TEXAS INSTRUMENTS, INC.                                                  *
*                                                                           *
*  NAME                                                                     *
*      convenc3 -- convenc3                                                 *
*                                                                           *
*                                                                           *
*  REVISION DATE                                                            *
*      04/15/2005                                                           *
*                                                                           *
*   USAGE                                                                   *
*       This routine is C-callable and can be called as:                    *
*                                                                           *
*       void convenc3_asm(unsigned int* in, unsigned int* out, int len,     *
*                         unsigned int Poly0, unsigned int Poly1, unsigned  *
*                                                                           *
*       in      =  input data                                               *
*       out     =  output data                                              *
*       len     =  number of input bits                                     *
*       Poly0   =  input of generator polynomial 0                          *
*       Poly1   =  input of generator polynomial 1                          *
*       Poly2   =  input of generator polynomial 2                          *
*                                                                           *
*   DESCRIPTION                                                             *
*       The following code implements rate 1/3, K=9 convolutional encoding. *
*       It will attach 8 tail zeros at the end of the input array.  So the  *
*       the size of the input array should be ceil( (nbits+8)/32 )          *
*                                                                           *
*   Performance                                                             *
*       Cycles:  14 + 3*ceil( (nbits+8)/32 )                                *
*       Size:    224 bytes                                                  *
*                                                                           *
*   MEMORY NOTE                                                             *
*       The optimized implementations are written for LITTLE ENDIAN.        *
*                                                                           *
*                                                                           *
* ------------------------------------------------------------------------- *
*             Copyright (c) 2005 Texas Instruments, Incorporated.           *
*                            All Rights Reserved.                           *
* ========================================================================= *


;******************************************************************************
;* FUNCTION NAME: convenc3_asm                                                *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,B0,B1,B2,B3,B4,B5,B6,B7,  *
;*                           A16,B16,B17,B18                                  *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,B0,B1,B2,B3,B4,B5,B6,B7,  *
;*                           A16,B16,B17,B18                                  *
;******************************************************************************

        .text
        .global _convenc3
_convenc3:
    .map    full_words/A3
    .map    p_in/A4
    .map    p_in'/A16
    .map    nbitsmod32/A1
    .map    reg0/B2
    .map    poly0/B4
    .map    poly1/B7
    .map    poly2/B5
    .map    out0/A3
    .map    out1/B0
    .map    tailpos_startend/A6
    .map    tailpos_startend'/B2
    .map    iw1/A6
    .map    nbits/A6
    .map    packed_ah/A3
    .map    in_previous/A1
    .map    reg31/A7
    .map    packed_bh/B1
    .map    reg24/B5
    .map    packed_al/A2
    .map    packed_al'/B6
    .map    packed_bl/B0
    .map    p_end/A2
    .map    iw/B18
    .map    iw'/A4
    .map    temp1/B6
    .map    temp1'/A7
    .map    temp2/B17
    .map    temp2'/A2
    .map    tailpos_end/A7
    .map    tailpos_start/B2
    .map    last_word/A5
    .map    g0h/B6
    .map    g1h/B2
    .map    g0l/A5
    .map    g2h/B2
    .map    g1l/A7
    .map    g2l/A5
    .map    p_out/A0
    .map    p_out'/B4
    .map    nbitsincltail/B2
    .map    cond/B0
    .map    full_wordsincltail/B5
    .map    words/A7
        .map    Poly0/B6
        .map    Poly1/A8
        .map    Poly2/B8
           SHR     .S1     nbits,0x5,full_words ; |28|
||         MV      .L1X    p_out',p_out      ; |3|
||         MV      .S2X    Poly1,poly1       ; |19|

           ADDAW   .D1     p_in,full_words,p_end ; |51|
||         MVK     .S1     0x1f,reg31        ; |22|
||         MV      .L1X    B3,A8             ; |3|

           LDW     .D1T1   *p_end,last_word  ; |52|
||         AND     .L1     nbits,reg31,nbitsmod32 ; |45|

           ADD     .L2X    0x8,nbits,nbitsincltail ; |42|
||         MVK     .S2     0x18,reg24        ; |23|

           SHR     .S2     nbitsincltail,0x5,full_wordsincltail ; |43|
||         SUB     .L2X    reg24,nbitsmod32,tailpos_start ; |46|

           SHL     .S2     tailpos_start,0x5,tailpos_startend' ; |48|

           CMPEQ   .L2X    full_words,full_wordsincltail,cond ; |44|
||         SUB     .L1     reg31,nbitsmod32,tailpos_end ; |47|

           ADD     .L1     0x1,full_words,words ; |29|
|| [!cond] CLR     .S1     last_word,tailpos_end,last_word ; |54|
||         OR      .D1X    tailpos_startend',tailpos_end,tailpos_startend ; |49|

   [!cond] ADD     .L1     2,full_words,words ; |29|
   [ cond] CLR     .S1     last_word,tailpos_startend,last_word ; |53|
           MVC     .S2X    words,ILC
           MV      .S2     Poly0,poly0       ; |18|

           STW     .D1T1   last_word,*p_end++ ; |55|
||         ZERO    .L2     reg0              ; |24|
||         ADD     .D2X    4,p_out,B16

   [!cond] STW     .D1T2   reg0,*p_end       ; |57|
||         MV      .S2     Poly2,poly2       ; |20|
||         ZERO    .L1     in_previous       ; |61|
||         ADD     .L2X    8,p_out,B3
||         MV      .S1     p_in,p_in'
;*----------------------------------------------------------------------------*
; PIPED LOOP PROLOG
;*----------------------------------------------------------------------------*
           SPLOOP  3       ;18               ; (P)
;** --------------------------------------------------------------------------*
; PIPED LOOP KERNEL
;** --------------------------------------------------------------------------*
           LDW     .D1T1   *p_in'++,iw'      ; |72| (P) <0,0>
           NOP             4

           MV      .D1     iw',in_previous   ; |74| (P) <0,5>
||         SHRMB   .L1     in_previous,iw',iw1 ; |73| (P) <0,5>

           XORMPY  .M1X    iw1,poly0,g0l     ; |89| (P) <0,6>

           SHL     .S2X    iw',0x8,iw        ; |75| (P) <0,7>
||         XORMPY  .M1X    iw1,poly1,g1l     ; |90| (P) <0,7>

           XORMPY  .M2     iw,poly2,g2h      ; |88| (P) <0,8>
||         XORMPY  .M1X    iw1,poly2,g2l     ; |91| (P) <0,8>

           XORMPY  .M2     iw,poly1,g1h      ; |87| (P) <0,9>
           XORMPY  .M2     iw,poly0,g0h      ; |86| (P) <0,10>
           PACKH2  .S1     g0l,g1l,temp1'    ; |102| (P) <0,11>

           SHRU    .S2     g2h,0x10,temp2    ; |106| (P) <0,12>
||         SHRU    .S1     g2l,0x10,temp2'   ; |103| (P) <0,12>

           SHFL3   .L1     temp1',temp2',packed_ah:packed_al ; |104| (P) <0,13>  ^
           PACKH2  .L2     g0h,g1h,temp1     ; |105| (P) <0,14>

           PACKLH2 .L1     packed_ah,packed_al,out0 ; |108| <0,15>
||         SHFL3   .L2     temp1,temp2,packed_bh:packed_bl ; |107| <0,15>
||         MV      .D2X    packed_al,packed_al' ; |104| <0,15>  ^ Define a twin register

           STW     .D1T1   out0,*p_out++(12) ; |111| <0,16>
||         STW     .D2T2   packed_bl,*B3++(12) ; |113| <0,16>
||         PACK2   .L2     packed_al',packed_bh,out1 ; |109| <0,16>

           SPKERNEL 3,1
||         STW     .D2T2   out1,*B16++(12)   ; |112| <0,17>

;** --------------------------------------------------------------------------*
; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
           RETNOP  .S2X    A8,5              ; |120|
           ; BRANCH OCCURS {A8}              ; |120|


                .end

* ======================================================================== *
*  End of file: convenc3.asm                                               *
* ------------------------------------------------------------------------ *
*          Copyright (C) 2005 Texas Instruments, Incorporated.             *
*                          All Rights Reserved.                            *
* ======================================================================== *