fir_cplx.asm

davinci技术 源码 视频监控汇编源码

||      MVC     .S2     B_NH,       RILC
||      SUB     .L1X    B_H_addr,   8,          A_H_addr
||      MV      .D2X    A_X_addr,   B_X_addr
||      SUB     .S1     A_j,        1,          A_j

  [A_j] SPLOOPD         4
||      SUB     .L1     A_X_addr,   8,          A_X_addr        ;
||      MVC     .S2     B_i0,       ILC
||      MV      .S1     B_NH,       A_NH
||      STDW    .D2T1   A13:A12,    *+B_SP[2]                   ; Save A13:A12

*- Stage 0 -----------------------------------------------------------------*
        LDDW    .D2T2   *++B_X_addr, B_dr3_di3:B_dr2_di2        ;[ 1,1]
||      LDDW    .D1T1   *++A_H_addr, A_cr1_ci1:A_cr0_ci0        ;[ 1,1]

        LDDW    .D1T1   *++A_X_addr, A_dr1_di1:A_dr0_di0        ;[ 2,1]

        LDW     .D2T2   *+B_X_addr[2], B_dr4_di4                ;[ 3,1]

        SPMASK
||^     ZERO    .L2     B_sr2:B_si2                             ;clear sums
||^     ZERO    .L1     A_sr0:A_si0                             ;clear sums
||^     ADD     .S2X    A_R_addr,   8,          B_R_addr
*- Stage 1 -----------------------------------------------------------------*
        SPMASK
||^     ZERO    .L2     B_p
||^     SUB     .L1     A_NH,       1,          A_NHC
||^     SUB     .S1     A_NH,       3,          A_NH            ;
||^     SUB     .S2     B_NH,       3,          B_NH            ;

        CMPY    .M2X    A_cr0_ci0,  B_dr2_di2,  B_p02r:B_p02i   ;[ 6,1]
||      CMPY    .M1X    A_cr1_ci1,  B_dr2_di2,  A_p12r:A_p12i   ;[ 6,1]

        CMPY    .M2X    A_cr1_ci1,  B_dr3_di3,  B_p13r:B_p13i   ;[ 7,1]
||      CMPY    .M1     A_cr0_ci0,  A_dr1_di1,  A_p01r:A_p01i   ;[ 7,1]

        SPMASK
||      CMPY    .M2X    A_cr1_ci1,  B_dr4_di4,  B_p14r:B_p14i   ;[ 8,1]
||      CMPY    .M1     A_cr0_ci0,  A_dr0_di0,  A_p00r:A_p00i   ;[ 8,1]
||^     ZERO    .L2     B_sr3:B_si3                             ;clear sums
||^     ZERO    .L1     A_sr1:A_si1                             ;clear sums
*- Stage 2 -----------------------------------------------------------------*
        CMPY    .M2X    A_cr0_ci0,  B_dr3_di3,  B_p03r:B_p03i   ;[ 9,1]
||      CMPY    .M1     A_cr1_ci1,  A_dr1_di1,  A_p11r:A_p11i   ;[ 9,1]

        NOP             1

        ADD     .S2     B_p02i,     B_p13i,     B_si2a          ;[11,1]
||      ADD     .L2     B_p02r,     B_p13r,     B_sr2a          ;[11,1]
||      ADD     .L1     A_p01i,     A_p12i,     A_si1a          ;[11,1]
||      ADD     .D1     A_p01r,     A_p12r,     A_sr1a          ;[11,1]

        ADD     .L2     B_si2,      B_si2a,     B_si2           ;[12,1]
||      SUB     .D2     B_sr2,      B_sr2a,     B_sr2           ;[12,1]
||      ADD     .D1     A_si1,      A_si1a,     A_si1           ;[12,1]
||      SUB     .L1     A_sr1,      A_sr1a,     A_sr1           ;[12,1]
*- Stage 3 -----------------------------------------------------------------*
        ADD     .L2     B_p03i,     B_p14i,     B_si3a          ;[13,1]
||      ADD     .S2     B_p03r,     B_p14r,     B_sr3a          ;[13,1]
||      ADD     .S1     A_p00i,     A_p11i,     A_si0a          ;[13,1]
||      ADD     .L1     A_p00r,     A_p11r,     A_sr0a          ;[13,1]

        ADD     .D2     B_si3,      B_si3a,     B_si3           ;[14,1]
||      SUB     .L2     B_sr3,      B_sr3a,     B_sr3           ;[14,1]
||      ADD     .L1     A_si0,      A_si0a,     A_si0           ;[14,1]
||      SUB     .S1     A_sr0,      A_sr0a,     A_sr0           ;[14,1]

        NOP

        SPKERNELR                                               ;
*---------------------------------------------------------------------------*
OUTER_LOOP:
* ER 0, PR 0
        ;
        SPMASK
||^     LDDW    .D2T2   *--B_X_addr[B_NH], B_dr3_di3:B_dr2_di2  ;adjust in ptr
||^     LDDW    .D1T1   *--A_H_addr[A_NHC], A_cr1_ci1:A_cr0_ci0 ;adjust coef ptr

        ; S2
        SPMASK
||^     LDDW    .D1T1   *--A_X_addr[A_NH], A_dr1_di1:A_dr0_di0  ;adjust in ptr

        ; S1
  [A_j] SUB     .S1     A_j,        1,          A_j             ;dec loop cnt

        ; S1,S2
        NOP             4
* ER 1, PR 1
        ;
;        NOP             1

        ; S2
;        NOP             1

        ; S1
;        NOP             1

        ; S1,S2
        SPMASK
||^     ADD     .S1     A_si1,      A_si1a,     A_si1_          ;
||^     SUB     .L1     A_sr1,      A_sr1a,     A_sr1_          ;
||^[B_p] STDW   .D1T1   A_sum1:A_sum0, *A_R_addr++[2]           ;store results
||^[B_p] STDW   .D2T2   B_sum3:B_sum2, *B_R_addr++[2]           ;store results
||      SUB     .S2     B_sr2,      B_sr2a,     B_sr2           ;

* ER 2, PR 2
        ;
        NOP             1

        ; S2
        RPACK2  .S2     B_si2,      B_sr2,      B_sum2

        ; S1
        SPMASK
||[A_j] B       .S1     OUTER_LOOP                              ;outer loop
||^     ADD     .S2     B_p02i,     B_p13i,     B_si2


        ; S1,S2 (Must use all L1,L2,D1,D2)
        SPMASK
||      RPACK2  .S1     A_si0,      A_sr0,      A_sum0
||      RPACK2  .S2     B_si3,      B_sr3,      B_sum3
||^     ADD     .D1     0,          A_si1a,     A_si1           ;[12,1]
||^     SUB     .L2     0,          B_sr2a,     B_sr2           ;[12,1]
||^     SUB     .L1     0,          A_sr1a,     A_sr1           ;[12,1]
||^     MVK     .D2     1,          B_p

* KRN
        SPMASK
||^     ADD     .L2     B_p03i,     B_p14i,     B_si3           ;
||^     ADD     .S1     A_p00i,     A_p11i,     A_si0           ;

        ; S2 (Must use all S1,D2,L1,L2)
        SPMASK
||^     RPACK2  .S1     A_si1_,     A_sr1_,     A_sum1
||^     MVK     .D2     1,          B_p
||^     SUB     .L2     0,          B_sr3a,     B_sr3           ;[14,1]
||^     SUB     .L1     0,          A_sr0a,     A_sr0           ;[14,1]

        ; S1
        NOP             2

        ; S1,S2
;       NOP
*---------------------------------------------------------------------------*
* End of the loops

* Outer loop code for last iteration
; EP 0
        NOP             4
; EP 1
        LDDW    .D2T1   *+B_SP[2],  A13:A12                     ; Restore A13:A12

        SPMASK
||^     LDDW    .D2T1   *B_SP++[4], A15:A14                     ; Restore B11:B10
||      ADD     .S2     B_si3,      B_si3a,     B_si3           ;[14,1]

        NOP

        RET     .S2     B_ret
; EP 2
        STDW    .D2T2   B_sum3:B_sum2, *B_R_addr++[2]
||      STDW    .D1T1   A_sum1:A_sum0, *A_R_addr++[2]

        NOP             1

        RPACK2  .S2     B_si2,      B_sr2,      B_sum2
||      RPACK2  .S1     A_si0,      A_sr0,      A_sum0

        RPACK2  .S2     B_si3,      B_sr3,      B_sum3
||      RPACK2  .S1     A_si1,      A_sr1,      A_sum1

;- after SPLOOP  ------------

        STDW    .D2T2   B_sum3:B_sum2, *B_R_addr
||      STDW    .D1T1   A_sum1:A_sum0, *A_R_addr


        .end

* ======================================================================== *
*  End of file: fir_cplx.asm                                               *
* ------------------------------------------------------------------------ *
*          Copyright (C) 2005 Texas Instruments, Incorporated.             *
*                          All Rights Reserved.                            *
* ======================================================================== *