fir_cplx.asm

davinci技术 源码 视频监控汇编源码

* ========================================================================= *
*  TEXAS INSTRUMENTS, INC.                                                  *
*                                                                           *
*  NAME                                                                     *
*      fir_cplx -- Complex block FIR                                        *
*                                                                           *
*                                                                           *
*  REVISION DATE                                                            *
*      09-May-2005                                                          *
*                                                                           *
*      USAGE                                                                *
*         This routine has following C prototype:                           *
*          void fir_cplx                                                    *
*          (                                                                *
*              const short *restrict x,                                     *
*              const short *restrict h,                                     *
*              short       *restrict r,                                     *
*              short                 nh,                                    *
*              short                 nr                                     *
*         )                                                                 *
*                                                                           *
*         x[2*(nr+nh-1)] : Complex input data. x must point to x[0].        *
*         h[2*nh]        : Complex coefficients (in reversed order).        *
*         r[2*nr]        : Complex output data.                             *
*         nh             : Number of complex coefficients.                  *
*                          Must be multiple of 4.                           *
*         nr             : Number of complex output samples.                *
*                          Must be multiple of 4.                           *
*                                                                           *
*                                                                           *
*                                                                           *
*      DESCRIPTION                                                          *
*         This complex FIR computes nr complex output samples using nh      *
*         complex coefficients. It operates on 16-bit data with a 32-bit    *
*         accumulate. Each array consists of an even and odd term with      *
*         even terms representing the real part of the element and the      *
*         odd terms the imaginary part. The pointer to input array x        *
*         must point to the first complex sample. The coefficients must     *
*         be stored in reversed order.                                      *
*                                                                           *
*                                                                           *
*                                                                           *
*     TECHNIQUES                                                            *
*        1.  The inner loop is unrolled 4 times and the outer loop is       *
*            unrolled 4 times, computing a multiple of 4 outputs.           *
*                                                                           *
*        2.  The inner and outer loops are completely overlaped with        *
*            SPLOOP reload; thus no overhead exists for outer loop          *
*            execution.                                                     *
*                                                                           *
*        3.  For a case where this function is used with circular           *
*            addressing, A4 and B7 are allocated to A_X_ptr and B_x_ptr,    *
*            respectively.                                                  *
*                                                                           *
*                                                                           *
*     ASSUMPTIONS                                                           *
*        Number of taps:    'nh' >= 16, multiple of 4.                      *
*        Number of samples: 'nr' >= 4, multiple of 4.                       *
*        Array 'r' is double-word aligned.                                  *
*                                                                           *
*                                                                           *
*     C CODE                                                                *
*        void fir_cplx                                                      *
*        (                                                                  *
*            const short *restrict x,                                       *
*            const short *restrict h,                                       *
*            short *restrict r,                                             *
*            short nh,                                                      *
*            short nr                                                       *
*        )                                                                  *
*        {                                                                  *
*          short i,j;                                                       *
*          int imag, real;                                                  *
*                                                                           *
*          for (i = 0; i < 2*nr; i += 2)                                    *
*          {                                                                *
*            imag = 0;                                                      *
*            real = 0;                                                      *
*            for (j = 0; j < 2*nh; j += 2)                                  *
*            {                                                              *
*              real += h[j+0] * x[i+j+0] - h[j+1] * x[i+j+1];               *
*              imag += h[j+1] * x[i+j+0] + h[j+0] * x[i+j+1];               *
*            }                                                              *
*            r[i]   = (real >> 15);                                         *
*            r[i+1] = (imag >> 15);                                         *
*          }                                                                *
*        }                                                                  *
*                                                                           *
*                                                                           *
*                                                                           *
*   NOTES                                                                   *
*      This function is fully interruptible.                                *
*      This function is a LITTLE ENDIAN implementation.                     *
*                                                                           *
*                                                                           *
*   CYCLES                                                                  *
*       nh * nr / 2 + 16                                                    *
*                                                                           *
*       For nh = 32 and nr = 256, cycles = 4112                             *
*                                                                           *
*   CODESIZE                                                                *
*       448 bytes                                                           *
*                                                                           *
* ------------------------------------------------------------------------- *
*             Copyright (c) 2005 Texas Instruments, Incorporated.           *
*                            All Rights Reserved.                           *
* ========================================================================= *


        .text
        .global _fir_cplx
_fir_cplx:                                                                
        .asg            A4,         A_X_addr
        .asg            B4,         B_H_addr
        .asg            A6,         A_R_addr
        .asg            B6,         B_NH
        .asg            A8,         A_NR

* ===================== SYMBOLIC REGISTER ASSIGNMENTS ===================== *
        .asg            A8,         A_H_addr
        .asg            B7,         B_X_addr
        .asg            A19,        A_NHC
        .asg            B27,        B_sr3
        .asg            B26,        B_si3
        .asg            B29,        B_sr2
        .asg            B28,        B_si2
        .asg            A27,        A_sr1
        .asg            A26,        A_si1
        .asg            A29,        A_sr0
        .asg            A28,        A_si0
        .asg            A31,        A_cr1_ci1
        .asg            A30,        A_cr0_ci0
        .asg            A25,        A_dr1_di1
        .asg            A24,        A_dr0_di0
        .asg            B31,        B_dr3_di3
        .asg            B30,        B_dr2_di2
        .asg            B22,        B_dr4_di4
        .asg            A23,        A_p00r
        .asg            A22,        A_p00i
        .asg            A21,        A_p11r
        .asg            A20,        A_p11i
        .asg            A21,        A_p01r
        .asg            A20,        A_p01i
        .asg            A23,        A_p12r
        .asg            A22,        A_p12i
        .asg            B25,        B_p02r
        .asg            B24,        B_p02i
        .asg            B23,        B_p13r
        .asg            B22,        B_p13i
        .asg            B23,        B_p03r
        .asg            B22,        B_p03i
        .asg            B25,        B_p14r
        .asg            B24,        B_p14i
        .asg            A24,        A_sr0a
        .asg            A25,        A_si0a
        .asg            A20,        A_sr1a
        .asg            A21,        A_si1a
        .asg            B23,        B_sr2a
        .asg            B30,        B_si2a
        .asg            B22,        B_sr3a
        .asg            B23,        B_si3a

        .asg            B3,         B_ret
        .asg            A16,        A_sum0
        .asg            A17,        A_sum1
        .asg            A0,         A_j
        .asg            A18,        A_NH
        .asg            A13,        A_sr1_
        .asg            A12,        A_si1_
        .asg            A14,        A_temp0
        .asg            A15,        A_temp1
        .asg            A9,         A_INaddr
        .asg            B20,        B_temp0
        .asg            B21,        B_temp1
        .asg            B16,        B_i0
        .asg            B18,        B_sum2
        .asg            B19,        B_sum3
        .asg            B17,        B_R_addr
        .asg            B0,         B_p
        .asg            B15,        B_SP


        SHR     .S2     B_NH,       1,          B_NH
||      SHR     .S1     A_NR,       2,          A_j
||      STDW    .D2T1   A15:A14,    *--B_SP[4]                  ; save A15:A15

        SUB     .L2     B_NH,       1,          B_i0