📄 idct_8x8.asm
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.asg B24, B_F53
.asg B31, B_F26x
.asg B30, B_F26
.asg B29, B_F04x
.asg B28, B_F04
.asg A25, A_F17
.asg A31, A_F53
.asg A20, A_F26
.asg A26, A_F04
.asg B31, B_Q1S1
.asg B24, B_Q0S0
.asg A28, A_Q1S1
.asg A26, A_Q0S0
.asg B26, B_p1p0
.asg B31, B_r1r0
.asg B8, B_g2h2
.asg B7, B_q0s0
.asg A24, A_p1p0
.asg A29, A_r1r0
.asg A16, A_g2h2
.asg A27, A_q0s0
.asg B27, B_g1g0
.asg B26, B_h1h0
.asg B22, B_h3g3
.asg A29, A_g1g0
.asg A28, A_h1h0
.asg A26, A_h3g3
.asg B31, B_h3h2
.asg B17, B_g3g2
.asg B25, B_f10
.asg B24, B_f67
.asg B27, B_f23
.asg B26, B_f54
.asg A9, A_h3h2
.asg A16, A_g3g2
.asg A25, A_f10
.asg A24, A_f67
.asg A29, A_f23
.asg A28, A_f54
.asg B27, B_f10a
.asg B28, B_f67a
.asg B7, B_f23a
.asg B27, B_f54a
.asg A31, A_f10a
.asg A27, A_f54a
.asg A29, A_f67a
.asg A28, A_f23a
.asg B27, B_f10r
.asg B23, B_f67r
.asg B29, B_f23r
.asg B30, B_f54r
.asg A27, A_f10r
.asg A27, A_f67r
.asg A25, A_f23r
.asg A31, A_f54r
.asg B17, B_f10s
.asg B8, B_f67s
.asg B16, B_f23s
.asg B24, B_f54s
.asg A28, A_f10s
.asg A30, A_f67s
.asg A9, A_f23s
.asg A28, A_f54s
.asg B27, B_f10t
.asg B26, B_f67t
.asg B9, B_f23t
.asg B28, B_f54t
.asg A30, A_f10t
.asg A30, A_f67t
.asg A27, A_f23t
.asg A26, A_f54t
.asg A27, A_f66t
.asg A26, A_f77t
.asg A25, A_f55t
.asg A24, A_f44t
.asg A27, A_f22t
.asg A26, A_f33t
.asg A31, A_f11t
.asg A30, A_f00t
* ========================================================================= *
.if $isdefed("NO_IEEE_1180_OME_CONTROL")
.asg ADD2, ADD_
.else
.asg ADD, ADD_
.endif
.asg 0x0101011D, cst_fix ; Pointer fixup constant
.asg 0x001F001F, cst_rnd ; Rounding value
; Following execute packet executed at the end of the epilog
; of the previous loop.
MVKL .S1 cst_rnd, A_rnd3
|| MVKL .S2 cst_fix, B_k_fix
SPLOOPD 12
|| MVC .S2 B_c, ILC
|| MV .L1 A_data, A_o_ptr
|| MV .L2 A_data, B_i_ptr
*- Stage 0 -----------------------------------------------------------------*
SPMASK
|| LDW .D2T2 *+B_i_ptr[4], B_F11 ;[ 1,1]
||^ MVKH .S1 cst_rnd, A_rnd3
||^ MVKH .S2 cst_fix, B_k_fix
LDW .D2T2 *+B_i_ptr[28], B_F77 ;[ 2,1]
LDW .D2T2 *+B_i_ptr[8], B_F22 ;[ 3,1]
LDW .D2T2 *+B_i_ptr[16], B_F44 ;[ 4,1]
|| SHR .S2 B_k_fix, 24, B_fx1 ;[ 4,1]
LDW .D2T2 *+B_i_ptr[24], B_F66 ;[ 5,1]
LDW .D2T2 *+B_i_ptr[12], B_F33 ;[ 6,1]
NOP 1
LDW .D2T2 *+B_i_ptr[20], B_F55 ;[ 8,1]
NOP 1
SPMASK
||^ MV B_k_fix, A_k_fix
DPACK2 .L2 B_F22, B_F66, B_F26x:B_F26 ;[11,1]
DPACK2 .L2 B_F11, B_F77, B_F17x:B_F17 ;[12,1]
|| LDW .D2T2 *B_i_ptr++[B_fx1], B_F00 ;[12,1]
|| ROTL .M2 B_k_fix, 8, B_k_fix ;[12,1]
*- Stage 1 -----------------------------------------------------------------*
DPACK2 .L2 B_F55, B_F33, B_F53x:B_F53 ;[13,1]
|| CMPYR1 .M2X B_F17, A_C71x, B_Q1S1 ;[13,1]
|| ROTL .M1X B_F26x, 0, A_F26 ;[13,1]
CMPYR1 .M2 B_F53, B_C35x, B_Q0S0 ;[14,1]
NOP 1
ROTL .M1X B_F53x, 0, A_F53 ;[16,1]
NOP 1
DPACK2 .L2 B_F00, B_F44, B_F04x:B_F04 ;[18,1]
|| ROTL .M1X B_F17x, 0, A_F17 ;[18,1]
SUB2 .L2 B_Q1S1, B_Q0S0, B_q0s0 ;[19,1]
CMPYR1 .M1 A_F17, A_C71x, A_Q1S1 ;[20,1]
CMPYR1 .M2X B_q0s0, A_C00nx, B_h3g3 ;[21,1]
|| CMPYR1 .M1X A_F53, B_C35x, A_Q0S0 ;[21,1]
CMPYR1 .M2 B_F26, B_C62x, B_r1r0 ;[22,1]
|| ROTL .M1X B_F04x, 0, A_F04 ;[22,1]
ADD2 .D2 B_Q1S1, B_Q0S0, B_g2h2 ;[23,1]
|| CMPYR1 .M1X A_F26, B_C62x, A_r1r0 ;[23,1]
|| CMPYR1 .M2X B_F04, A_C44x, B_p1p0 ;[23,1]
CMPYR1 .M1 A_F04, A_C44x, A_p1p0 ;[24,1]
*- Stage 2 -----------------------------------------------------------------*
SUB2 .L1 A_Q1S1, A_Q0S0, A_q0s0 ;[25,1]
|| ADD2 .D1 A_Q1S1, A_Q0S0, A_g2h2 ;[25,1]
PACKLH2 .L2 B_h3g3, B_g2h2, B_g3g2 ;[26,1]
|| CMPYR1 .M1 A_q0s0, A_C00nx, A_h3g3 ;[26,1]
PACKHL2 .S2 B_h3g3, B_g2h2, B_h3h2 ;[27,1]
|| ADDSUB2 .L2 B_p1p0, B_r1r0, B_g1g0:B_h1h0 ;[27,1]
ADDSUB2 .L2 B_g1g0, B_h3h2, B_f10:B_f67 ;[28,1]
|| ADDSUB2 .L1 A_p1p0, A_r1r0, A_g1g0:A_h1h0 ;[28,1]
ADD_ .L2 B_f67, B_f67, B_f67a ;[29,1]
|| ADD_ .S2 B_f10, B_f10, B_f10a ;[29,1]
ADD_ .S2X B_f67a, A_rnd3, B_f67r ;[30,1]
|| PACKHL2 .L1 A_h3g3, A_g2h2, A_h3h2 ;[30,1]
SADD2 .S2 B_f67r, B_f67r, B_f67s ;[31,1]
|| ADD_ .D2X B_f10a, A_rnd3, B_f10r ;[31,1]
|| PACKLH2 .S1 A_h3g3, A_g2h2, A_g3g2 ;[31,1]
SADD2 .S2 B_f10r, B_f10r, B_f10s ;[32,1]
|| ADDSUB2 .L1 A_g1g0, A_h3h2, A_f10:A_f67 ;[32,1]
|| ADDSUB2 .L2 B_h1h0, B_g3g2, B_f23:B_f54 ;[32,1]
SHR2 .S2 B_f67s, 7, B_f67t ;[33,1]
|| ADD_ .S1 A_f67, A_f67, A_f67a ;[33,1]
|| ADD_ .L1 A_f10, A_f10, A_f10a ;[33,1]
|| ADD_ .D2 B_f54, B_f54, B_f54a ;[33,1]
|| ADD_ .L2 B_f23, B_f23, B_f23a ;[33,1]
SHR2 .S2 B_f10s, 7, B_f10t ;[34,1]
|| ADD_ .S1 A_f67a, A_rnd3, A_f67r ;[34,1]
|| ADD_ .D2X B_f54a, A_rnd3, B_f54r ;[34,1]
|| ADD_ .L2X B_f23a, A_rnd3, B_f23r ;[34,1]
|| ADDSUB2 .L1 A_h1h0, A_g3g2, A_f23:A_f54 ;[34,1]
SADD2 .S1 A_f67r, A_f67r, A_f67s ;[35,1]
|| SADD2 .S2 B_f54r, B_f54r, B_f54s ;[35,1]
|| ADD_ .L1 A_f54, A_f54, A_f54a ;[35,1]
SHR2 .S1 A_f67s, 7, A_f67t ;[36,1]
|| SADD2 .S2 B_f23r, B_f23r, B_f23s ;[36,1]
|| ADD_ .L1 A_f54a, A_rnd3, A_f54r ;[36,1]
|| ADD_ .D1 A_f10a, A_rnd3, A_f10r ;[36,1]
*- Stage 3 -----------------------------------------------------------------*
SHR2 .S2 B_f54s, 7, B_f54t ;[37,1]
|| SADD2 .S1 A_f10r, A_f10r, A_f10s ;[37,1]
DPACK2 .L1X A_f67t, B_f67t, A_f66t:A_f77t ;[38,1]
|| SHR2 .S1 A_f10s, 7, A_f10t ;[38,1]
|| SHR2 .S2 B_f23s, 7, B_f23t ;[38,1]
|| ADD_ .D1 A_f23, A_f23, A_f23a ;[38,1]
DPACK2 .L1X A_f10t, B_f10t, A_f11t:A_f00t ;[39,1]
|| SADD2 .S1 A_f54r, A_f54r, A_f54s ;[39,1]
|| ADD_ .D1 A_f23a, A_rnd3, A_f23r ;[39,1]
STW .D1T1 A_f77t, *+A_o_ptr[28] ;[40,1]
|| SHR2 .S1 A_f54s, 7, A_f54t ;[40,1]
STW .D1T1 A_f11t, *+A_o_ptr[4] ;[41,1]
|| DPACK2 .L1X A_f54t, B_f54t, A_f55t:A_f44t ;[41,1]
|| SADD2 .S1 A_f23r, A_f23r, A_f23s ;[41,1]
STW .D1T1 A_f66t, *+A_o_ptr[24] ;[42,1]
|| SHR2 .S1 A_f23s, 7, A_f23t ;[42,1]
STW .D1T1 A_f55t, *+A_o_ptr[20] ;[43,1]
|| DPACK2 .L1X A_f23t, B_f23t, A_f22t:A_f33t ;[43,1]
|| ROTL .M1 A_k_fix, 8, A_k_fix ;[43,1]
STW .D1T1 A_f44t, *+A_o_ptr[16] ;[44,1]
|| SHR .S1 A_k_fix, 24, A_fx2 ;[44,1]
STW .D1T1 A_f22t, *+A_o_ptr[8] ;[45,1]
STW .D1T1 A_f33t, *+A_o_ptr[12] ;[46,1]
SPKERNEL 2, 5
|| STW .D1T1 A_f00t, *A_o_ptr++[A_fx2] ;[47,1]
; Branch happens at the end of the epilog.
; Do not add NOPs.
B .S2 B_ret
.end
* ======================================================================== *
* End of file: idct_8x8.asm *
* ------------------------------------------------------------------------ *
* Copyright (C) 2005 Texas Instruments, Incorporated. *
* All Rights Reserved. *
* ======================================================================== *
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