📄 io_map.h
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#define IRQSC_IRQEDG _IRQSC.Bits.IRQEDG
#define IRQSC_IRQPDD _IRQSC.Bits.IRQPDD
#define IRQSC_IRQMOD_MASK 0x01
#define IRQSC_IRQIE_MASK 0x02
#define IRQSC_IRQACK_MASK 0x04
#define IRQSC_IRQF_MASK 0x08
#define IRQSC_IRQPE_MASK 0x10
#define IRQSC_IRQEDG_MASK 0x20
#define IRQSC_IRQPDD_MASK 0x40
/*** TPM1SC - TPM 1 Status and Control Register; 0x00000020 ***/
typedef union {
byte Byte;
struct {
byte PS0 :1; /* Prescale Divisor Select Bit 0 */
byte PS1 :1; /* Prescale Divisor Select Bit 1 */
byte PS2 :1; /* Prescale Divisor Select Bit 2 */
byte CLKSA :1; /* Clock Source Select A */
byte CLKSB :1; /* Clock Source Select B */
byte CPWMS :1; /* Center-Aligned PWM Select */
byte TOIE :1; /* Timer Overflow Interrupt Enable */
byte TOF :1; /* Timer Overflow Flag */
} Bits;
struct {
byte grpPS :3;
byte grpCLKSx :2;
byte :1;
byte :1;
byte :1;
} MergedBits;
} TPM1SCSTR;
extern volatile TPM1SCSTR _TPM1SC @0x00000020;
#define TPM1SC _TPM1SC.Byte
#define TPM1SC_PS0 _TPM1SC.Bits.PS0
#define TPM1SC_PS1 _TPM1SC.Bits.PS1
#define TPM1SC_PS2 _TPM1SC.Bits.PS2
#define TPM1SC_CLKSA _TPM1SC.Bits.CLKSA
#define TPM1SC_CLKSB _TPM1SC.Bits.CLKSB
#define TPM1SC_CPWMS _TPM1SC.Bits.CPWMS
#define TPM1SC_TOIE _TPM1SC.Bits.TOIE
#define TPM1SC_TOF _TPM1SC.Bits.TOF
#define TPM1SC_PS _TPM1SC.MergedBits.grpPS
#define TPM1SC_CLKSx _TPM1SC.MergedBits.grpCLKSx
#define TPM1SC_PS0_MASK 0x01
#define TPM1SC_PS1_MASK 0x02
#define TPM1SC_PS2_MASK 0x04
#define TPM1SC_CLKSA_MASK 0x08
#define TPM1SC_CLKSB_MASK 0x10
#define TPM1SC_CPWMS_MASK 0x20
#define TPM1SC_TOIE_MASK 0x40
#define TPM1SC_TOF_MASK 0x80
#define TPM1SC_PS_MASK 0x07
#define TPM1SC_PS_BITNUM 0x00
#define TPM1SC_CLKSx_MASK 0x18
#define TPM1SC_CLKSx_BITNUM 0x03
/*** TPM1CNT - TPM 1 Counter Register; 0x00000021 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPM1CNTH - TPM 1 Counter Register High; 0x00000021 ***/
union {
byte Byte;
} TPM1CNTHSTR;
#define TPM1CNTH _TPM1CNT.Overlap_STR.TPM1CNTHSTR.Byte
/*** TPM1CNTL - TPM 1 Counter Register Low; 0x00000022 ***/
union {
byte Byte;
} TPM1CNTLSTR;
#define TPM1CNTL _TPM1CNT.Overlap_STR.TPM1CNTLSTR.Byte
} Overlap_STR;
} TPM1CNTSTR;
extern volatile TPM1CNTSTR _TPM1CNT @0x00000021;
#define TPM1CNT _TPM1CNT.Word
/*** TPM1MOD - TPM 1 Timer Counter Modulo Register; 0x00000023 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPM1MODH - TPM 1 Timer Counter Modulo Register High; 0x00000023 ***/
union {
byte Byte;
} TPM1MODHSTR;
#define TPM1MODH _TPM1MOD.Overlap_STR.TPM1MODHSTR.Byte
/*** TPM1MODL - TPM 1 Timer Counter Modulo Register Low; 0x00000024 ***/
union {
byte Byte;
} TPM1MODLSTR;
#define TPM1MODL _TPM1MOD.Overlap_STR.TPM1MODLSTR.Byte
} Overlap_STR;
} TPM1MODSTR;
extern volatile TPM1MODSTR _TPM1MOD @0x00000023;
#define TPM1MOD _TPM1MOD.Word
/*** TPM1C0SC - TPM 1 Timer Channel 0 Status and Control Register; 0x00000025 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte ELS0A :1; /* Edge/Level Select Bit A */
byte ELS0B :1; /* Edge/Level Select Bit B */
byte MS0A :1; /* Mode Select A for TPM Channel 0 */
byte MS0B :1; /* Mode Select B for TPM Channel 0 */
byte CH0IE :1; /* Channel 0 Interrupt Enable */
byte CH0F :1; /* Channel 0 Flag */
} Bits;
struct {
byte :1;
byte :1;
byte grpELS0x :2;
byte grpMS0x :2;
byte :1;
byte :1;
} MergedBits;
} TPM1C0SCSTR;
extern volatile TPM1C0SCSTR _TPM1C0SC @0x00000025;
#define TPM1C0SC _TPM1C0SC.Byte
#define TPM1C0SC_ELS0A _TPM1C0SC.Bits.ELS0A
#define TPM1C0SC_ELS0B _TPM1C0SC.Bits.ELS0B
#define TPM1C0SC_MS0A _TPM1C0SC.Bits.MS0A
#define TPM1C0SC_MS0B _TPM1C0SC.Bits.MS0B
#define TPM1C0SC_CH0IE _TPM1C0SC.Bits.CH0IE
#define TPM1C0SC_CH0F _TPM1C0SC.Bits.CH0F
#define TPM1C0SC_ELS0x _TPM1C0SC.MergedBits.grpELS0x
#define TPM1C0SC_MS0x _TPM1C0SC.MergedBits.grpMS0x
#define TPM1C0SC_ELS0A_MASK 0x04
#define TPM1C0SC_ELS0B_MASK 0x08
#define TPM1C0SC_MS0A_MASK 0x10
#define TPM1C0SC_MS0B_MASK 0x20
#define TPM1C0SC_CH0IE_MASK 0x40
#define TPM1C0SC_CH0F_MASK 0x80
#define TPM1C0SC_ELS0x_MASK 0x0C
#define TPM1C0SC_ELS0x_BITNUM 0x02
#define TPM1C0SC_MS0x_MASK 0x30
#define TPM1C0SC_MS0x_BITNUM 0x04
/*** TPM1C0V - TPM 1 Timer Channel 0 Value Register; 0x00000026 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPM1C0VH - TPM 1 Timer Channel 0 Value Register High; 0x00000026 ***/
union {
byte Byte;
} TPM1C0VHSTR;
#define TPM1C0VH _TPM1C0V.Overlap_STR.TPM1C0VHSTR.Byte
/*** TPM1C0VL - TPM 1 Timer Channel 0 Value Register Low; 0x00000027 ***/
union {
byte Byte;
} TPM1C0VLSTR;
#define TPM1C0VL _TPM1C0V.Overlap_STR.TPM1C0VLSTR.Byte
} Overlap_STR;
} TPM1C0VSTR;
extern volatile TPM1C0VSTR _TPM1C0V @0x00000026;
#define TPM1C0V _TPM1C0V.Word
/*** TPM1C1SC - TPM 1 Timer Channel 1 Status and Control Register; 0x00000028 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte ELS1A :1; /* Edge/Level Select Bit A */
byte ELS1B :1; /* Edge/Level Select Bit B */
byte MS1A :1; /* Mode Select A for TPM Channel 1 */
byte MS1B :1; /* Mode Select B for TPM Channel 1 */
byte CH1IE :1; /* Channel 1 Interrupt Enable */
byte CH1F :1; /* Channel 1 Flag */
} Bits;
struct {
byte :1;
byte :1;
byte grpELS1x :2;
byte grpMS1x :2;
byte :1;
byte :1;
} MergedBits;
} TPM1C1SCSTR;
extern volatile TPM1C1SCSTR _TPM1C1SC @0x00000028;
#define TPM1C1SC _TPM1C1SC.Byte
#define TPM1C1SC_ELS1A _TPM1C1SC.Bits.ELS1A
#define TPM1C1SC_ELS1B _TPM1C1SC.Bits.ELS1B
#define TPM1C1SC_MS1A _TPM1C1SC.Bits.MS1A
#define TPM1C1SC_MS1B _TPM1C1SC.Bits.MS1B
#define TPM1C1SC_CH1IE _TPM1C1SC.Bits.CH1IE
#define TPM1C1SC_CH1F _TPM1C1SC.Bits.CH1F
#define TPM1C1SC_ELS1x _TPM1C1SC.MergedBits.grpELS1x
#define TPM1C1SC_MS1x _TPM1C1SC.MergedBits.grpMS1x
#define TPM1C1SC_ELS1A_MASK 0x04
#define TPM1C1SC_ELS1B_MASK 0x08
#define TPM1C1SC_MS1A_MASK 0x10
#define TPM1C1SC_MS1B_MASK 0x20
#define TPM1C1SC_CH1IE_MASK 0x40
#define TPM1C1SC_CH1F_MASK 0x80
#define TPM1C1SC_ELS1x_MASK 0x0C
#define TPM1C1SC_ELS1x_BITNUM 0x02
#define TPM1C1SC_MS1x_MASK 0x30
#define TPM1C1SC_MS1x_BITNUM 0x04
/*** TPM1C1V - TPM 1 Timer Channel 1 Value Register; 0x00000029 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPM1C1VH - TPM 1 Timer Channel 1 Value Register High; 0x00000029 ***/
union {
byte Byte;
} TPM1C1VHSTR;
#define TPM1C1VH _TPM1C1V.Overlap_STR.TPM1C1VHSTR.Byte
/*** TPM1C1VL - TPM 1 Timer Channel 1 Value Register Low; 0x0000002A ***/
union {
byte Byte;
} TPM1C1VLSTR;
#define TPM1C1VL _TPM1C1V.Overlap_STR.TPM1C1VLSTR.Byte
} Overlap_STR;
} TPM1C1VSTR;
extern volatile TPM1C1VSTR _TPM1C1V @0x00000029;
#define TPM1C1V _TPM1C1V.Word
/*** TPM1C2SC - TPM 1 Timer Channel 2 Status and Control Register; 0x0000002B ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte ELS2A :1; /* Edge/Level Select Bit A */
byte ELS2B :1; /* Edge/Level Select Bit B */
byte MS2A :1; /* Mode Select A for TPM Channel 2 */
byte MS2B :1; /* Mode Select B for TPM Channel 2 */
byte CH2IE :1; /* Channel 2 Interrupt Enable */
byte CH2F :1; /* Channel 2 Flag */
} Bits;
struct {
byte :1;
byte :1;
byte grpELS2x :2;
byte grpMS2x :2;
byte :1;
byte :1;
} MergedBits;
} TPM1C2SCSTR;
extern volatile TPM1C2SCSTR _TPM1C2SC @0x0000002B;
#define TPM1C2SC _TPM1C2SC.Byte
#define TPM1C2SC_ELS2A _TPM1C2SC.Bits.ELS2A
#define TPM1C2SC_ELS2B _TPM1C2SC.Bits.ELS2B
#define TPM1C2SC_MS2A _TPM1C2SC.Bits.MS2A
#define TPM1C2SC_MS⌨️ 快捷键说明
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