📄 stm32f10x_usart.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 903] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_usart.o --depend=.\Obj\stm32f10x_usart.d --device=DARMSTM --apcs=interwork -O2 -I..\..\..\FWLib\library\inc -I..\..\include -IC:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DVECT_TAB_FLASH --omf_browse=.\Obj\stm32f10x_usart.crf ..\..\..\FWLib\library\src\stm32f10x_usart.c]
THUMB
AREA ||i.USART_DeInit||, CODE, READONLY, ALIGN=2
USART_DeInit PROC
;;;88 {
;;;89 switch (*(u32*)&USARTx)
000000 4911 LDR r1,|L1.72|
000002 b510 PUSH {r4,lr}
000004 1840 ADDS r0,r0,r1
000006 d010 BEQ |L1.42|
000008 f5b0f5b0 CMP r0,#0x400
00000c d010 BEQ |L1.48|
00000e f5b0f5b0 CMP r0,#0xf400
000012 d118 BNE |L1.70|
;;;90 {
;;;91 case USART1_BASE:
;;;92 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
000014 2101 MOVS r1,#1
000016 038c LSLS r4,r1,#14
000018 4620 MOV r0,r4
00001a f7fff7ff BL RCC_APB2PeriphResetCmd
;;;93 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
00001e 4620 MOV r0,r4
000020 e8bde8bd POP {r4,lr}
000024 2100 MOVS r1,#0
000026 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.42|
;;;94 break;
;;;95
;;;96 case USART2_BASE:
;;;97 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
00002a 2101 MOVS r1,#1
00002c 044c LSLS r4,r1,#17
;;;98 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
;;;99 break;
00002e e001 B |L1.52|
|L1.48|
;;;100
;;;101 case USART3_BASE:
;;;102 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
000030 2101 MOVS r1,#1
000032 048c LSLS r4,r1,#18
|L1.52|
000034 4620 MOV r0,r4
000036 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;103 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
00003a 4620 MOV r0,r4
00003c e8bde8bd POP {r4,lr}
000040 2100 MOVS r1,#0
000042 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.70|
;;;104 break;
;;;105
;;;106 default:
;;;107 break;
;;;108 }
;;;109 }
000046 bd10 POP {r4,pc}
ENDP
|L1.72|
000048 bfffbc00 DCD 0xbfffbc00
AREA ||i.USART_Init||, CODE, READONLY, ALIGN=2
USART_Init PROC
;;;122 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
;;;123 {
000000 b530 PUSH {r4,r5,lr}
000002 4605 MOV r5,r0
;;;124 u32 tmpreg = 0x00, apbclock = 0x00;
;;;125 u32 integerdivider = 0x00;
;;;126 u32 fractionaldivider = 0x00;
;;;127 RCC_ClocksTypeDef RCC_ClocksStatus;
;;;128
;;;129 /* Check the parameters */
;;;130 assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
;;;131 assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
;;;132 assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
;;;133 assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
;;;134 assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
;;;135 assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
;;;136 assert_param(IS_USART_CLOCK(USART_InitStruct->USART_Clock));
;;;137 assert_param(IS_USART_CPOL(USART_InitStruct->USART_CPOL));
;;;138 assert_param(IS_USART_CPHA(USART_InitStruct->USART_CPHA));
;;;139 assert_param(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit));
;;;140
;;;141 /*---------------------------- USART CR2 Configuration -----------------------*/
;;;142 tmpreg = USARTx->CR2;
000004 8a00 LDRH r0,[r0,#0x10]
000006 b085 SUB sp,sp,#0x14
000008 460c MOV r4,r1
;;;143 /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */
;;;144 tmpreg &= CR2_CLEAR_Mask;
00000a f24cf24c MOV r1,#0xc0ff
00000e 4008 ANDS r0,r0,r1
;;;145
;;;146 /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
;;;147 /* Set STOP[13:12] bits according to USART_Mode value */
;;;148 /* Set CPOL bit according to USART_CPOL value */
;;;149 /* Set CPHA bit according to USART_CPHA value */
;;;150 /* Set LBCL bit according to USART_LastBit value */
;;;151 tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock |
000010 88e1 LDRH r1,[r4,#6]
000012 89e2 LDRH r2,[r4,#0xe]
000014 8a63 LDRH r3,[r4,#0x12]
000016 4311 ORRS r1,r1,r2
000018 8a22 LDRH r2,[r4,#0x10]
00001a 431a ORRS r2,r2,r3
00001c 4311 ORRS r1,r1,r2
00001e 8aa2 LDRH r2,[r4,#0x14]
000020 4311 ORRS r1,r1,r2
000022 4301 ORRS r1,r1,r0
;;;152 USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA |
;;;153 USART_InitStruct->USART_LastBit;
;;;154
;;;155 /* Write to USART CR2 */
;;;156 USARTx->CR2 = (u16)tmpreg;
000024 8229 STRH r1,[r5,#0x10]
;;;157
;;;158 /*---------------------------- USART CR1 Configuration -----------------------*/
;;;159 tmpreg = 0x00;
;;;160 tmpreg = USARTx->CR1;
000026 89a8 LDRH r0,[r5,#0xc]
;;;161 /* Clear M, PCE, PS, TE and RE bits */
;;;162 tmpreg &= CR1_CLEAR_Mask;
000028 f64ef64e MOV r1,#0xe9f3
00002c 4008 ANDS r0,r0,r1
;;;163
;;;164 /* Configure the USART Word Length, Parity and mode ----------------------- */
;;;165 /* Set the M bits according to USART_WordLength value */
;;;166 /* Set PCE and PS bits according to USART_Parity value */
;;;167 /* Set TE and RE bits according to USART_Mode value */
;;;168 tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
00002e 88a1 LDRH r1,[r4,#4]
000030 8922 LDRH r2,[r4,#8]
000032 4311 ORRS r1,r1,r2
000034 89a2 LDRH r2,[r4,#0xc]
000036 4302 ORRS r2,r2,r0
000038 4311 ORRS r1,r1,r2
;;;169 USART_InitStruct->USART_Mode;
;;;170
;;;171 /* Write to USART CR1 */
;;;172 USARTx->CR1 = (u16)tmpreg;
00003a 81a9 STRH r1,[r5,#0xc]
;;;173
;;;174 /*---------------------------- USART CR3 Configuration -----------------------*/
;;;175 tmpreg = 0x00;
;;;176 tmpreg = USARTx->CR3;
00003c 8aa8 LDRH r0,[r5,#0x14]
;;;177 /* Clear CTSE and RTSE bits */
;;;178 tmpreg &= CR3_CLEAR_Mask;
00003e f64ff64f MOV r1,#0xfcff
000042 4008 ANDS r0,r0,r1
;;;179
;;;180 /* Configure the USART HFC -------------------------------------------------*/
;;;181 /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
;;;182 tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
000044 8961 LDRH r1,[r4,#0xa]
000046 4301 ORRS r1,r1,r0
;;;183
;;;184 /* Write to USART CR3 */
;;;185 USARTx->CR3 = (u16)tmpreg;
000048 82a9 STRH r1,[r5,#0x14]
;;;186
;;;187 /*---------------------------- USART BRR Configuration -----------------------*/
;;;188 tmpreg = 0x00;
;;;189
;;;190 /* Configure the USART Baud Rate -------------------------------------------*/
;;;191 RCC_GetClocksFreq(&RCC_ClocksStatus);
00004a 4668 MOV r0,sp
00004c f7fff7ff BL RCC_GetClocksFreq
;;;192 if ((*(u32*)&USARTx) == USART1_BASE)
000050 4810 LDR r0,|L2.148|
000052 4285 CMP r5,r0
000054 d101 BNE |L2.90|
;;;193 {
;;;194 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
000056 9803 LDR r0,[sp,#0xc]
000058 e000 B |L2.92|
|L2.90|
;;;195 }
;;;196 else
;;;197 {
;;;198 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
00005a 9802 LDR r0,[sp,#8]
|L2.92|
;;;199 }
;;;200
;;;201 /* Determine the integer part */
;;;202 integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
00005c 2119 MOVS r1,#0x19
00005e 4348 MULS r0,r1,r0
000060 6821 LDR r1,[r4,#0]
;;;203 tmpreg = (integerdivider / 0x64) << 0x04;
000062 2264 MOVS r2,#0x64
000064 0089 LSLS r1,r1,#2
000066 fbb0fbb0 UDIV r0,r0,r1
00006a fbb0fbb0 UDIV r1,r0,r2
00006e 0109 LSLS r1,r1,#4
;;;204
;;;205 /* Determine the fractional part */
;;;206 fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
000070 090b LSRS r3,r1,#4
000072 f06ff06f MVN r4,#0x18
000076 4363 MULS r3,r4,r3
000078 eb00eb00 ADD r0,r0,r3,LSL #2
;;;207 tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
00007c 2332 MOVS r3,#0x32
00007e eb03eb03 ADD r0,r3,r0,LSL #4
000082 fbb0fbb0 UDIV r0,r0,r2
000086 f000f000 AND r0,r0,#0xf
00008a 4308 ORRS r0,r0,r1
;;;208
;;;209 /* Write to USART BRR */
;;;210 USARTx->BRR = (u16)tmpreg;
00008c 8128 STRH r0,[r5,#8]
;;;211 }
00008e b005 ADD sp,sp,#0x14
000090 bd30 POP {r4,r5,pc}
ENDP
000092 0000 DCW 0x0000
|L2.148|
000094 40013800 DCD 0x40013800
AREA ||i.USART_StructInit||, CODE, READONLY, ALIGN=1
USART_StructInit PROC
;;;223 /* USART_InitStruct members default value */
;;;224 USART_InitStruct->USART_BaudRate = 0x2580; /* 9600 Baud */
000000 f44ff44f MOV r1,#0x2580
;;;225 USART_InitStruct->USART_WordLength = USART_WordLength_8b;
000004 6001 STR r1,[r0,#0]
000006 2100 MOVS r1,#0
000008 8081 STRH r1,[r0,#4]
;;;226 USART_InitStruct->USART_StopBits = USART_StopBits_1;
00000a 80c1 STRH r1,[r0,#6]
;;;227 USART_InitStruct->USART_Parity = USART_Parity_No ;
00000c 8101 STRH r1,[r0,#8]
;;;228 USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
00000e 8141 STRH r1,[r0,#0xa]
;;;229 USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
000010 220c MOVS r2,#0xc
000012 8182 STRH r2,[r0,#0xc]
;;;230 USART_InitStruct->USART_Clock = USART_Clock_Disable;
000014 81c1 STRH r1,[r0,#0xe]
;;;231 USART_InitStruct->USART_CPOL = USART_CPOL_Low;
000016 8201 STRH r1,[r0,#0x10]
;;;232 USART_InitStruct->USART_CPHA = USART_CPHA_1Edge;
000018 8241 STRH r1,[r0,#0x12]
;;;233 USART_InitStruct->USART_LastBit = USART_LastBit_Disable;
00001a 8281 STRH r1,[r0,#0x14]
;;;234 }
00001c 4770 BX lr
ENDP
AREA ||i.USART_Cmd||, CODE, READONLY, ALIGN=1
USART_Cmd PROC
;;;250
;;;251 if (NewState != DISABLE)
000000 2900 CMP r1,#0
;;;252 {
;;;253 /* Enable the selected USART by setting the RUN bit in the CR1 register */
;;;254 USARTx->CR1 |= CR1_RUN_Set;
000002 8981 LDRH r1,[r0,#0xc]
000004 d002 BEQ |L4.12|
000006 f441f441 ORR r1,r1,#0x2000
00000a e001 B |L4.16|
|L4.12|
;;;255 }
;;;256 else
;;;257 {
;;;258 /* Disable the selected USART by clearing the RUN bit in the CR1 register */
;;;259 USARTx->CR1 &= CR1_RUN_Reset;
00000c f421f421 BIC r1,r1,#0x2000
|L4.16|
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