📄 stm32f10x_rcc.txt
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;;;728
;;;729 /* HCLK clock frequency */
;;;730 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00004a 6801 LDR r1,[r0,#0]
00004c 40e1 LSRS r1,r1,r4
;;;731
;;;732 /* Get PCLK1 prescaler */
;;;733 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
00004e 6041 STR r1,[r0,#4]
000050 6854 LDR r4,[r2,#4]
000052 f404f404 AND r4,r4,#0x700
;;;734 tmp = tmp >> 8;
000056 0a24 LSRS r4,r4,#8
;;;735 presc = APBAHBPrescTable[tmp];
000058 5d1c LDRB r4,[r3,r4]
;;;736
;;;737 /* PCLK1 clock frequency */
;;;738 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00005a fa21fa21 LSR r4,r1,r4
;;;739
;;;740 /* Get PCLK2 prescaler */
;;;741 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
00005e 6084 STR r4,[r0,#8]
000060 6854 LDR r4,[r2,#4]
000062 f404f404 AND r4,r4,#0x3800
;;;742 tmp = tmp >> 11;
000066 0ae4 LSRS r4,r4,#11
;;;743 presc = APBAHBPrescTable[tmp];
000068 5d1b LDRB r3,[r3,r4]
;;;744
;;;745 /* PCLK2 clock frequency */
;;;746 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00006a 40d9 LSRS r1,r1,r3
;;;747
;;;748 /* Get ADCCLK prescaler */
;;;749 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
00006c 60c1 STR r1,[r0,#0xc]
00006e 6852 LDR r2,[r2,#4]
;;;750 tmp = tmp >> 14;
;;;751 presc = ADCPrescTable[tmp];
000070 4b07 LDR r3,|L21.144|
000072 f402f402 AND r2,r2,#0xc000
000076 0b92 LSRS r2,r2,#14
000078 1f1b SUBS r3,r3,#4
00007a 5c9a LDRB r2,[r3,r2]
;;;752
;;;753 /* ADCCLK clock frequency */
;;;754 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
00007c fbb1fbb1 UDIV r1,r1,r2
;;;755 }
000080 6101 STR r1,[r0,#0x10]
000082 bd30 POP {r4,r5,pc}
ENDP
|L21.132|
000084 40021000 DCD 0x40021000
|L21.136|
000088 007a1200 DCD 0x007a1200
|L21.140|
00008c 003d0900 DCD 0x003d0900
|L21.144|
000090 00000004 DCD ||.constdata||+0x4
AREA ||i.RCC_AHBPeriphClockCmd||, CODE, READONLY, ALIGN=2
RCC_AHBPeriphClockCmd PROC
;;;771 void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
;;;772 {
000000 4a04 LDR r2,|L22.20|
;;;773 /* Check the parameters */
;;;774 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
;;;775 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;776
;;;777 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;778 {
;;;779 RCC->AHBENR |= RCC_AHBPeriph;
000004 6951 LDR r1,[r2,#0x14]
000006 d001 BEQ |L22.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L22.14|
|L22.12|
;;;780 }
;;;781 else
;;;782 {
;;;783 RCC->AHBENR &= ~RCC_AHBPeriph;
00000c 4381 BICS r1,r1,r0
|L22.14|
00000e 6151 STR r1,[r2,#0x14]
;;;784 }
;;;785 }
000010 4770 BX lr
ENDP
000012 0000 DCW 0x0000
|L22.20|
000014 40021000 DCD 0x40021000
AREA ||i.RCC_APB2PeriphClockCmd||, CODE, READONLY, ALIGN=2
RCC_APB2PeriphClockCmd PROC
;;;802 void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
;;;803 {
000000 4a04 LDR r2,|L23.20|
;;;804 /* Check the parameters */
;;;805 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;806 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;807
;;;808 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;809 {
;;;810 RCC->APB2ENR |= RCC_APB2Periph;
000004 6991 LDR r1,[r2,#0x18]
000006 d001 BEQ |L23.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L23.14|
|L23.12|
;;;811 }
;;;812 else
;;;813 {
;;;814 RCC->APB2ENR &= ~RCC_APB2Periph;
00000c 4381 BICS r1,r1,r0
|L23.14|
00000e 6191 STR r1,[r2,#0x18]
;;;815 }
;;;816 }
000010 4770 BX lr
ENDP
000012 0000 DCW 0x0000
|L23.20|
000014 40021000 DCD 0x40021000
AREA ||i.RCC_APB1PeriphClockCmd||, CODE, READONLY, ALIGN=2
RCC_APB1PeriphClockCmd PROC
;;;834 void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
;;;835 {
000000 4a04 LDR r2,|L24.20|
;;;836 /* Check the parameters */
;;;837 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;838 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;839
;;;840 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;841 {
;;;842 RCC->APB1ENR |= RCC_APB1Periph;
000004 69d1 LDR r1,[r2,#0x1c]
000006 d001 BEQ |L24.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L24.14|
|L24.12|
;;;843 }
;;;844 else
;;;845 {
;;;846 RCC->APB1ENR &= ~RCC_APB1Periph;
00000c 4381 BICS r1,r1,r0
|L24.14|
00000e 61d1 STR r1,[r2,#0x1c]
;;;847 }
;;;848 }
000010 4770 BX lr
ENDP
000012 0000 DCW 0x0000
|L24.20|
000014 40021000 DCD 0x40021000
AREA ||i.RCC_APB2PeriphResetCmd||, CODE, READONLY, ALIGN=2
RCC_APB2PeriphResetCmd PROC
;;;864 void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
;;;865 {
000000 4a04 LDR r2,|L25.20|
;;;866 /* Check the parameters */
;;;867 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;868 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;869
;;;870 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;871 {
;;;872 RCC->APB2RSTR |= RCC_APB2Periph;
000004 68d1 LDR r1,[r2,#0xc]
000006 d001 BEQ |L25.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L25.14|
|L25.12|
;;;873 }
;;;874 else
;;;875 {
;;;876 RCC->APB2RSTR &= ~RCC_APB2Periph;
00000c 4381 BICS r1,r1,r0
|L25.14|
00000e 60d1 STR r1,[r2,#0xc]
;;;877 }
;;;878 }
000010 4770 BX lr
ENDP
000012 0000 DCW 0x0000
|L25.20|
000014 40021000 DCD 0x40021000
AREA ||i.RCC_APB1PeriphResetCmd||, CODE, READONLY, ALIGN=2
RCC_APB1PeriphResetCmd PROC
;;;895 void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
;;;896 {
000000 4a04 LDR r2,|L26.20|
;;;897 /* Check the parameters */
;;;898 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;899 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;900
;;;901 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;902 {
;;;903 RCC->APB1RSTR |= RCC_APB1Periph;
000004 6911 LDR r1,[r2,#0x10]
000006 d001 BEQ |L26.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L26.14|
|L26.12|
;;;904 }
;;;905 else
;;;906 {
;;;907 RCC->APB1RSTR &= ~RCC_APB1Periph;
00000c 4381 BICS r1,r1,r0
|L26.14|
00000e 6111 STR r1,[r2,#0x10]
;;;908 }
;;;909 }
000010 4770 BX lr
ENDP
000012 0000 DCW 0x0000
|L26.20|
000014 40021000 DCD 0x40021000
AREA ||i.RCC_BackupResetCmd||, CODE, READONLY, ALIGN=2
RCC_BackupResetCmd PROC
;;;919 void RCC_BackupResetCmd(FunctionalState NewState)
;;;920 {
000000 4901 LDR r1,|L27.8|
;;;921 /* Check the parameters */
;;;922 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;923
;;;924 *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;925 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L27.8|
000008 42420440 DCD 0x42420440
AREA ||i.RCC_ClockSecuritySystemCmd||, CODE, READONLY, ALIGN=2
RCC_ClockSecuritySystemCmd PROC
;;;939
;;;940 *(vu32 *) CR_CSSON_BB = (u32)NewState;
000000 4901 LDR r1,|L28.8|
000002 64c8 STR r0,[r1,#0x4c]
;;;941 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L28.8|
000008 42420000 DCD 0x42420000
AREA ||i.RCC_MCOConfig||, CODE, READONLY, ALIGN=2
RCC_MCOConfig PROC
;;;961 /* Perform Byte access to MCO[26:24] bits to select the MCO source */
;;;962 *(vu8 *) 0x40021007 = RCC_MCO;
000000 4901 LDR r1,|L29.8|
000002 71c8 STRB r0,[r1,#7]
;;;963 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L29.8|
000008 40021000 DCD 0x40021000
AREA ||i.RCC_ClearFlag||, CODE, READONLY, ALIGN=2
RCC_ClearFlag PROC
;;;1037 /* Set RMVF bit to clear the reset flags */
;;;1038 RCC->CSR |= CSR_RMVF_Set;
000000 4802 LDR r0,|L30.12|
000002 6a41 LDR r1,[r0,#0x24]
000004 f041f041 ORR r1,r1,#0x1000000
000008 6241 STR r1,[r0,#0x24]
;;;1039 }
00000a 4770 BX lr
ENDP
|L30.12|
00000c 40021000 DCD 0x40021000
AREA ||i.RCC_GetITStatus||, CODE, READONLY, ALIGN=2
RCC_GetITStatus PROC
;;;1062 /* Check the status of the specified RCC interrupt */
;;;1063 if ((RCC->CIR & RCC_IT) != (u32)RESET)
000000 4903 LDR r1,|L31.16|
000002 4602 MOV r2,r0
000004 6889 LDR r1,[r1,#8]
000006 2000 MOVS r0,#0
000008 4211 TST r1,r2
00000a d000 BEQ |L31.14|
;;;1064 {
;;;1065 bitstatus = SET;
00000c 2001 MOVS r0,#1
|L31.14|
;;;1066 }
;;;1067 else
;;;1068 {
;;;1069 bitstatus = RESET;
;;;1070 }
;;;1071
;;;1072 /* Return the RCC_IT status */
;;;1073 return bitstatus;
;;;1074 }
00000e 4770 BX lr
ENDP
|L31.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_ClearITPendingBit||, CODE, READONLY, ALIGN=2
RCC_ClearITPendingBit PROC
;;;1096 pending bits */
;;;1097 *(vu8 *) 0x4002100A = RCC_IT;
000000 4901 LDR r1,|L32.8|
000002 7288 STRB r0,[r1,#0xa]
;;;1098 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L32.8|
000008 40021000 DCD 0x40021000
AREA ||.data||, DATA, ALIGN=2
HSEStatus
000000 00000000 DCB 0x00,0x00,0x00,0x00
StartUpCounter
000004 00000000 DCD 0x00000000
AREA ||.constdata||, DATA, READONLY, ALIGN=0
ADCPrescTable
000000 02040608 DCB 0x02,0x04,0x06,0x08
APBAHBPrescTable
000004 00000000 DCB 0x00,0x00,0x00,0x00
000008 01020304 DCB 0x01,0x02,0x03,0x04
00000c 01020304 DCB 0x01,0x02,0x03,0x04
000010 06070809 DCB 0x06,0x07,0x08,0x09
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