📄 stm32f10x_rcc.txt
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000002 6840 LDR r0,[r0,#4]
000004 f000f000 AND r0,r0,#0xc
;;;375 }
000008 4770 BX lr
ENDP
00000a 0000 DCW 0x0000
|L10.12|
00000c 40021000 DCD 0x40021000
AREA ||i.RCC_HCLKConfig||, CODE, READONLY, ALIGN=2
RCC_HCLKConfig PROC
;;;401
;;;402 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L11.16|
000002 6851 LDR r1,[r2,#4]
;;;403
;;;404 /* Clear HPRE[7:4] bits */
;;;405 tmpreg &= CFGR_HPRE_Reset_Mask;
000004 f021f021 BIC r1,r1,#0xf0
;;;406
;;;407 /* Set HPRE[7:4] bits according to RCC_HCLK value */
;;;408 tmpreg |= RCC_HCLK;
000008 4301 ORRS r1,r1,r0
;;;409
;;;410 /* Store the new value */
;;;411 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;412 }
00000c 4770 BX lr
ENDP
00000e 0000 DCW 0x0000
|L11.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_PCLK1Config||, CODE, READONLY, ALIGN=2
RCC_PCLK1Config PROC
;;;434
;;;435 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L12.16|
000002 6851 LDR r1,[r2,#4]
;;;436
;;;437 /* Clear PPRE1[10:8] bits */
;;;438 tmpreg &= CFGR_PPRE1_Reset_Mask;
000004 f421f421 BIC r1,r1,#0x700
;;;439
;;;440 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
;;;441 tmpreg |= RCC_PCLK1;
000008 4301 ORRS r1,r1,r0
;;;442
;;;443 /* Store the new value */
;;;444 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;445 }
00000c 4770 BX lr
ENDP
00000e 0000 DCW 0x0000
|L12.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_PCLK2Config||, CODE, READONLY, ALIGN=2
RCC_PCLK2Config PROC
;;;467
;;;468 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L13.16|
000002 6851 LDR r1,[r2,#4]
;;;469
;;;470 /* Clear PPRE2[13:11] bits */
;;;471 tmpreg &= CFGR_PPRE2_Reset_Mask;
000004 f421f421 BIC r1,r1,#0x3800
;;;472
;;;473 /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
;;;474 tmpreg |= RCC_PCLK2 << 3;
000008 ea41ea41 ORR r0,r1,r0,LSL #3
;;;475
;;;476 /* Store the new value */
;;;477 RCC->CFGR = tmpreg;
00000c 6050 STR r0,[r2,#4]
;;;478 }
00000e 4770 BX lr
ENDP
|L13.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_ITConfig||, CODE, READONLY, ALIGN=2
RCC_ITConfig PROC
;;;496 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
;;;497 {
000000 4a04 LDR r2,|L14.20|
;;;498 /* Check the parameters */
;;;499 assert_param(IS_RCC_IT(RCC_IT));
;;;500 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;501
;;;502 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;503 {
;;;504 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
;;;505 *(vu8 *) 0x40021009 |= RCC_IT;
000004 7a51 LDRB r1,[r2,#9]
000006 d001 BEQ |L14.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L14.14|
|L14.12|
;;;506 }
;;;507 else
;;;508 {
;;;509 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
;;;510 *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
00000c 4381 BICS r1,r1,r0
|L14.14|
00000e 7251 STRB r1,[r2,#9]
;;;511 }
;;;512 }
000010 4770 BX lr
ENDP
000012 0000 DCW 0x0000
|L14.20|
000014 40021000 DCD 0x40021000
AREA ||i.RCC_USBCLKConfig||, CODE, READONLY, ALIGN=2
RCC_USBCLKConfig PROC
;;;527 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
;;;528 {
000000 4901 LDR r1,|L15.8|
;;;529 /* Check the parameters */
;;;530 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
;;;531
;;;532 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
000002 6008 STR r0,[r1,#0]
;;;533 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L15.8|
000008 424200d8 DCD 0x424200d8
AREA ||i.RCC_ADCCLKConfig||, CODE, READONLY, ALIGN=2
RCC_ADCCLKConfig PROC
;;;554
;;;555 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L16.16|
000002 6851 LDR r1,[r2,#4]
;;;556
;;;557 /* Clear ADCPRE[15:14] bits */
;;;558 tmpreg &= CFGR_ADCPRE_Reset_Mask;
000004 f421f421 BIC r1,r1,#0xc000
;;;559
;;;560 /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
;;;561 tmpreg |= RCC_ADCCLK;
000008 4301 ORRS r1,r1,r0
;;;562
;;;563 /* Store the new value */
;;;564 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;565 }
00000c 4770 BX lr
ENDP
00000e 0000 DCW 0x0000
|L16.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_LSEConfig||, CODE, READONLY, ALIGN=2
RCC_LSEConfig PROC
;;;585 /* Reset LSEON bit */
;;;586 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
000000 4906 LDR r1,|L17.28|
000002 2200 MOVS r2,#0
000004 700a STRB r2,[r1,#0]
;;;587
;;;588 /* Reset LSEBYP bit */
;;;589 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
000006 f801f801 STRB r2,[r1],#-0x20
;;;590
;;;591 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;592 switch(RCC_LSE)
00000a 2801 CMP r0,#1
00000c d002 BEQ |L17.20|
00000e 2804 CMP r0,#4
000010 d102 BNE |L17.24|
;;;593 {
;;;594 case RCC_LSE_ON:
;;;595 /* Set LSEON bit */
;;;596 *(vu8 *) BDCR_BASE = RCC_LSE_ON;
;;;597 break;
;;;598
;;;599 case RCC_LSE_Bypass:
;;;600 /* Set LSEBYP and LSEON bits */
;;;601 *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
000012 2005 MOVS r0,#5
|L17.20|
000014 f881f881 STRB r0,[r1,#0x20]
|L17.24|
;;;602 break;
;;;603
;;;604 default:
;;;605 break;
;;;606 }
;;;607 }
000018 4770 BX lr
ENDP
00001a 0000 DCW 0x0000
|L17.28|
00001c 40021020 DCD 0x40021020
AREA ||i.RCC_LSICmd||, CODE, READONLY, ALIGN=2
RCC_LSICmd PROC
;;;618 void RCC_LSICmd(FunctionalState NewState)
;;;619 {
000000 4901 LDR r1,|L18.8|
;;;620 /* Check the parameters */
;;;621 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;622
;;;623 *(vu32 *) CSR_LSION_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;624 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L18.8|
000008 42420480 DCD 0x42420480
AREA ||i.RCC_RTCCLKConfig||, CODE, READONLY, ALIGN=2
RCC_RTCCLKConfig PROC
;;;645 /* Select the RTC clock source */
;;;646 RCC->BDCR |= RCC_RTCCLKSource;
000000 4a02 LDR r2,|L19.12|
000002 6a11 LDR r1,[r2,#0x20]
000004 4301 ORRS r1,r1,r0
000006 6211 STR r1,[r2,#0x20]
;;;647 }
000008 4770 BX lr
ENDP
00000a 0000 DCW 0x0000
|L19.12|
00000c 40021000 DCD 0x40021000
AREA ||i.RCC_RTCCLKCmd||, CODE, READONLY, ALIGN=2
RCC_RTCCLKCmd PROC
;;;659 void RCC_RTCCLKCmd(FunctionalState NewState)
;;;660 {
000000 4901 LDR r1,|L20.8|
;;;661 /* Check the parameters */
;;;662 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;663
;;;664 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;665 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L20.8|
000008 4242043c DCD 0x4242043c
AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2
RCC_GetClocksFreq PROC
;;;675 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
;;;676 {
000000 b530 PUSH {r4,r5,lr}
;;;677 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
;;;678
;;;679 /* Get SYSCLK source -------------------------------------------------------*/
;;;680 tmp = RCC->CFGR & CFGR_SWS_Mask;
000002 4a20 LDR r2,|L21.132|
000004 6851 LDR r1,[r2,#4]
000006 4b20 LDR r3,|L21.136|
000008 f011f011 ANDS r1,r1,#0xc
;;;681
;;;682 switch (tmp)
00000c d003 BEQ |L21.22|
00000e 2904 CMP r1,#4
000010 d001 BEQ |L21.22|
000012 2908 CMP r1,#8
000014 d001 BEQ |L21.26|
|L21.22|
;;;683 {
;;;684 case 0x00: /* HSI used as system clock */
;;;685 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
;;;686 break;
000016 6003 STR r3,[r0,#0]
000018 e011 B |L21.62|
|L21.26|
;;;687
;;;688 case 0x04: /* HSE used as system clock */
;;;689 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
;;;690 break;
;;;691
;;;692 case 0x08: /* PLL used as system clock */
;;;693 /* Get PLL clock source and multiplication factor ----------------------*/
;;;694 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00001a 6851 LDR r1,[r2,#4]
;;;695 pllmull = ( pllmull >> 18) + 2;
00001c 2402 MOVS r4,#2
00001e f401f401 AND r1,r1,#0x3c0000
000022 eb04eb04 ADD r1,r4,r1,LSR #18
;;;696
;;;697 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
000026 6854 LDR r4,[r2,#4]
000028 4d18 LDR r5,|L21.140|
00002a f414f414 TST r4,#0x10000
;;;698
;;;699 if (pllsource == 0x00)
00002e d002 BEQ |L21.54|
;;;700 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;701 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
;;;702 }
;;;703 else
;;;704 {/* HSE selected as PLL clock entry */
;;;705
;;;706 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
000030 6854 LDR r4,[r2,#4]
000032 03a4 LSLS r4,r4,#14
000034 d501 BPL |L21.58|
|L21.54|
000036 4369 MULS r1,r5,r1
000038 e000 B |L21.60|
|L21.58|
;;;707 {/* HSE oscillator clock divided by 2 */
;;;708
;;;709 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
;;;710 }
;;;711 else
;;;712 {
;;;713 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
00003a 4359 MULS r1,r3,r1
|L21.60|
00003c 6001 STR r1,[r0,#0]
|L21.62|
;;;714 }
;;;715 }
;;;716 break;
;;;717
;;;718 default:
;;;719 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
;;;720 break;
;;;721 }
;;;722
;;;723 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;724 /* Get HCLK prescaler */
;;;725 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
00003e 6851 LDR r1,[r2,#4]
;;;726 tmp = tmp >> 4;
;;;727 presc = APBAHBPrescTable[tmp];
000040 4b13 LDR r3,|L21.144|
000042 f001f001 AND r1,r1,#0xf0
000046 0909 LSRS r1,r1,#4
000048 5c5c LDRB r4,[r3,r1]
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