📄 stm32f10x_rcc.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 903] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_rcc.o --depend=.\Obj\stm32f10x_rcc.d --device=DARMSTM --apcs=interwork -O2 -I..\..\..\FWLib\library\inc -I..\..\include -IC:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DVECT_TAB_FLASH --omf_browse=.\Obj\stm32f10x_rcc.crf ..\..\..\FWLib\library\src\stm32f10x_rcc.c]
THUMB
AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;124 /* Disable APB2 Peripheral Reset */
;;;125 RCC->APB2RSTR = 0x00000000;
000000 480e LDR r0,|L1.60|
000002 2100 MOVS r1,#0
000004 60c1 STR r1,[r0,#0xc]
;;;126
;;;127 /* Disable APB1 Peripheral Reset */
;;;128 RCC->APB1RSTR = 0x00000000;
000006 6101 STR r1,[r0,#0x10]
;;;129
;;;130 /* FLITF and SRAM Clock ON */
;;;131 RCC->AHBENR = 0x00000014;
000008 2214 MOVS r2,#0x14
00000a 6142 STR r2,[r0,#0x14]
;;;132
;;;133 /* Disable APB2 Peripheral Clock */
;;;134 RCC->APB2ENR = 0x00000000;
00000c 6181 STR r1,[r0,#0x18]
;;;135
;;;136 /* Disable APB1 Peripheral Clock */
;;;137 RCC->APB1ENR = 0x00000000;
00000e 61c1 STR r1,[r0,#0x1c]
;;;138
;;;139 /* Set HSION bit */
;;;140 RCC->CR |= (u32)0x00000001;
000010 6802 LDR r2,[r0,#0]
000012 f042f042 ORR r2,r2,#1
000016 6002 STR r2,[r0,#0]
;;;141
;;;142 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
;;;143 RCC->CFGR &= 0xF8FF0000;
000018 6842 LDR r2,[r0,#4]
00001a 4b09 LDR r3,|L1.64|
00001c 401a ANDS r2,r2,r3
00001e 6042 STR r2,[r0,#4]
;;;144
;;;145 /* Reset HSEON, CSSON and PLLON bits */
;;;146 RCC->CR &= 0xFEF6FFFF;
000020 6802 LDR r2,[r0,#0]
000022 4b08 LDR r3,|L1.68|
000024 401a ANDS r2,r2,r3
000026 6002 STR r2,[r0,#0]
;;;147
;;;148 /* Reset HSEBYP bit */
;;;149 RCC->CR &= 0xFFFBFFFF;
000028 6802 LDR r2,[r0,#0]
00002a f422f422 BIC r2,r2,#0x40000
00002e 6002 STR r2,[r0,#0]
;;;150
;;;151 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;152 RCC->CFGR &= 0xFF80FFFF;
000030 6842 LDR r2,[r0,#4]
000032 f422f422 BIC r2,r2,#0x7f0000
000036 6042 STR r2,[r0,#4]
;;;153
;;;154 /* Disable all interrupts */
;;;155 RCC->CIR = 0x00000000;
000038 6081 STR r1,[r0,#8]
;;;156 }
00003a 4770 BX lr
ENDP
|L1.60|
00003c 40021000 DCD 0x40021000
|L1.64|
000040 f8ff0000 DCD 0xf8ff0000
|L1.68|
000044 fef6ffff DCD 0xfef6ffff
AREA ||i.RCC_HSEConfig||, CODE, READONLY, ALIGN=2
RCC_HSEConfig PROC
;;;178 /* Reset HSEON bit */
;;;179 RCC->CR &= CR_HSEON_Reset;
000000 490b LDR r1,|L2.48|
000002 680a LDR r2,[r1,#0]
000004 f422f422 BIC r2,r2,#0x10000
000008 600a STR r2,[r1,#0]
;;;180
;;;181 /* Reset HSEBYP bit */
;;;182 RCC->CR &= CR_HSEBYP_Reset;
00000a 680a LDR r2,[r1,#0]
00000c f422f422 BIC r2,r2,#0x40000
000010 600a STR r2,[r1,#0]
;;;183
;;;184 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;185 switch(RCC_HSE)
000012 f5b0f5b0 CMP r0,#0x10000
000016 d007 BEQ |L2.40|
000018 f5b0f5b0 CMP r0,#0x40000
00001c d103 BNE |L2.38|
;;;186 {
;;;187 case RCC_HSE_ON:
;;;188 /* Set HSEON bit */
;;;189 RCC->CR |= CR_HSEON_Set;
;;;190 break;
;;;191
;;;192 case RCC_HSE_Bypass:
;;;193 /* Set HSEBYP and HSEON bits */
;;;194 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
00001e 6808 LDR r0,[r1,#0]
000020 f440f440 ORR r0,r0,#0x50000
|L2.36|
000024 6008 STR r0,[r1,#0]
|L2.38|
;;;195 break;
;;;196
;;;197 default:
;;;198 break;
;;;199 }
;;;200 }
000026 4770 BX lr
|L2.40|
000028 6808 LDR r0,[r1,#0]
00002a f440f440 ORR r0,r0,#0x10000
00002e e7f9 B |L2.36|
ENDP
|L2.48|
000030 40021000 DCD 0x40021000
AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2
RCC_GetFlagStatus PROC
;;;984 FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
;;;985 {
000000 4603 MOV r3,r0
;;;986 u32 tmp = 0;
;;;987 u32 statusreg = 0;
;;;988 FlagStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;989
;;;990 /* Check the parameters */
;;;991 assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;992
;;;993 /* Get the RCC register index */
;;;994 tmp = RCC_FLAG >> 5;
000004 0959 LSRS r1,r3,#5
000006 4a09 LDR r2,|L3.44|
;;;995
;;;996 if (tmp == 1) /* The flag to check is in CR register */
000008 2901 CMP r1,#1
00000a d101 BNE |L3.16|
;;;997 {
;;;998 statusreg = RCC->CR;
00000c 6811 LDR r1,[r2,#0]
00000e e004 B |L3.26|
|L3.16|
;;;999 }
;;;1000 else if (tmp == 2) /* The flag to check is in BDCR register */
000010 2902 CMP r1,#2
000012 d101 BNE |L3.24|
;;;1001 {
;;;1002 statusreg = RCC->BDCR;
000014 6a11 LDR r1,[r2,#0x20]
000016 e000 B |L3.26|
|L3.24|
;;;1003 }
;;;1004 else /* The flag to check is in CSR register */
;;;1005 {
;;;1006 statusreg = RCC->CSR;
000018 6a51 LDR r1,[r2,#0x24]
|L3.26|
;;;1007 }
;;;1008
;;;1009 /* Get the flag position */
;;;1010 tmp = RCC_FLAG & FLAG_Mask;
00001a f003f003 AND r2,r3,#0x1f
;;;1011
;;;1012 if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
00001e 2301 MOVS r3,#1
000020 4093 LSLS r3,r3,r2
000022 420b TST r3,r1
000024 d000 BEQ |L3.40|
;;;1013 {
;;;1014 bitstatus = SET;
000026 2001 MOVS r0,#1
|L3.40|
;;;1015 }
;;;1016 else
;;;1017 {
;;;1018 bitstatus = RESET;
;;;1019 }
;;;1020
;;;1021 /* Return the flag status */
;;;1022 return bitstatus;
;;;1023 }
000028 4770 BX lr
ENDP
00002a 0000 DCW 0x0000
|L3.44|
00002c 40021000 DCD 0x40021000
AREA ||i.RCC_WaitForHSEStartUp||, CODE, READONLY, ALIGN=2
RCC_WaitForHSEStartUp PROC
;;;211 ErrorStatus RCC_WaitForHSEStartUp(void)
;;;212 {
000000 b510 PUSH {r4,lr}
000002 4c0a LDR r4,|L4.44|
|L4.4|
;;;213 /* Wait till HSE is ready and if Time out is reached exit */
;;;214 do
;;;215 {
;;;216 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
000004 2031 MOVS r0,#0x31
000006 f7fff7ff BL RCC_GetFlagStatus
00000a 7020 STRB r0,[r4,#0] ; HSEStatus
;;;217 StartUpCounter++;
00000c 6860 LDR r0,[r4,#4] ; StartUpCounter
00000e 1c40 ADDS r0,r0,#1
000010 6060 STR r0,[r4,#4] ; StartUpCounter
;;;218 } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
000012 7820 LDRB r0,[r4,#0] ; HSEStatus
000014 b910 CBNZ r0,|L4.28|
000016 6860 LDR r0,[r4,#4] ; StartUpCounter
000018 28ff CMP r0,#0xff
00001a d1f3 BNE |L4.4|
|L4.28|
;;;219
;;;220
;;;221 if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00001c 2031 MOVS r0,#0x31
00001e f7fff7ff BL RCC_GetFlagStatus
000022 2800 CMP r0,#0
000024 d000 BEQ |L4.40|
;;;222 {
;;;223 return SUCCESS;
000026 2001 MOVS r0,#1
|L4.40|
;;;224 }
;;;225 else
;;;226 {
;;;227 return ERROR;
;;;228 }
;;;229 }
000028 bd10 POP {r4,pc}
ENDP
00002a 0000 DCW 0x0000
|L4.44|
00002c 00000000 DCD ||.data||
AREA ||i.RCC_AdjustHSICalibrationValue||, CODE, READONLY, ALIGN=2
RCC_AdjustHSICalibrationValue PROC
;;;246
;;;247 tmpreg = RCC->CR;
000000 4a03 LDR r2,|L5.16|
000002 6811 LDR r1,[r2,#0]
;;;248
;;;249 /* Clear HSITRIM[7:3] bits */
;;;250 tmpreg &= CR_HSITRIM_Mask;
000004 f021f021 BIC r1,r1,#0xf8
;;;251
;;;252 /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
;;;253 tmpreg |= (u32)HSICalibrationValue << 3;
000008 ea41ea41 ORR r0,r1,r0,LSL #3
;;;254
;;;255 /* Store the new value */
;;;256 RCC->CR = tmpreg;
00000c 6010 STR r0,[r2,#0]
;;;257 }
00000e 4770 BX lr
ENDP
|L5.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_HSICmd||, CODE, READONLY, ALIGN=2
RCC_HSICmd PROC
;;;273
;;;274 *(vu32 *) CR_HSION_BB = (u32)NewState;
000000 4901 LDR r1,|L6.8|
000002 6008 STR r0,[r1,#0]
;;;275 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L6.8|
000008 42420000 DCD 0x42420000
AREA ||i.RCC_PLLConfig||, CODE, READONLY, ALIGN=2
RCC_PLLConfig PROC
;;;301
;;;302 tmpreg = RCC->CFGR;
000000 4b03 LDR r3,|L7.16|
000002 685a LDR r2,[r3,#4]
;;;303
;;;304 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
;;;305 tmpreg &= CFGR_PLL_Mask;
;;;306
;;;307 /* Set the PLL configuration bits */
;;;308 tmpreg |= RCC_PLLSource | RCC_PLLMul;
000004 4308 ORRS r0,r0,r1
000006 f422f422 BIC r2,r2,#0x3f0000
00000a 4310 ORRS r0,r0,r2
;;;309
;;;310 /* Store the new value */
;;;311 RCC->CFGR = tmpreg;
00000c 6058 STR r0,[r3,#4]
;;;312 }
00000e 4770 BX lr
ENDP
|L7.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_PLLCmd||, CODE, READONLY, ALIGN=2
RCC_PLLCmd PROC
;;;327
;;;328 *(vu32 *) CR_PLLON_BB = (u32)NewState;
000000 4901 LDR r1,|L8.8|
000002 6608 STR r0,[r1,#0x60]
;;;329 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L8.8|
000008 42420000 DCD 0x42420000
AREA ||i.RCC_SYSCLKConfig||, CODE, READONLY, ALIGN=2
RCC_SYSCLKConfig PROC
;;;348
;;;349 tmpreg = RCC->CFGR;
000000 4a03 LDR r2,|L9.16|
000002 6851 LDR r1,[r2,#4]
;;;350
;;;351 /* Clear SW[1:0] bits */
;;;352 tmpreg &= CFGR_SW_Mask;
000004 f021f021 BIC r1,r1,#3
;;;353
;;;354 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;355 tmpreg |= RCC_SYSCLKSource;
000008 4301 ORRS r1,r1,r0
;;;356
;;;357 /* Store the new value */
;;;358 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;359 }
00000c 4770 BX lr
ENDP
00000e 0000 DCW 0x0000
|L9.16|
000010 40021000 DCD 0x40021000
AREA ||i.RCC_GetSYSCLKSource||, CODE, READONLY, ALIGN=2
RCC_GetSYSCLKSource PROC
;;;373 {
;;;374 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
000000 4802 LDR r0,|L10.12|
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