📄 stm32f10x_nvic.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 903] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_nvic.o --depend=.\Obj\stm32f10x_nvic.d --device=DARMSTM --apcs=interwork -O2 -I..\..\..\FWLib\library\inc -I..\..\include -IC:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DVECT_TAB_FLASH --omf_browse=.\Obj\stm32f10x_nvic.crf ..\..\..\FWLib\library\src\stm32f10x_nvic.c]
THUMB
AREA ||i.NVIC_DeInit||, CODE, READONLY, ALIGN=1
NVIC_DeInit PROC
;;;37 {
;;;38 u32 index = 0;
000000 2000 MOVS r0,#0
;;;39
;;;40 NVIC->ICER[0] = 0xFFFFFFFF;
000002 1e43 SUBS r3,r0,#1
000004 f04ff04f MOV r1,#0xe000e000
000008 f8c1f8c1 STR r3,[r1,#0x180]
;;;41 NVIC->ICER[1] = 0x000007FF;
00000c 0d5a LSRS r2,r3,#21
00000e f8c1f8c1 STR r2,[r1,#0x184]
;;;42 NVIC->ICPR[0] = 0xFFFFFFFF;
000012 f8c1f8c1 STR r3,[r1,#0x280]
;;;43 NVIC->ICPR[1] = 0x000007FF;
000016 f8c1f8c1 STR r2,[r1,#0x284]
00001a 4602 MOV r2,r0
|L1.28|
;;;44
;;;45 for(index = 0; index < 0x0B; index++)
;;;46 {
;;;47 NVIC->IPR[index] = 0x00000000;
00001c eb01eb01 ADD r3,r1,r0,LSL #2
000020 f8c3f8c3 STR r2,[r3,#0x400]
000024 1c40 ADDS r0,r0,#1
000026 280b CMP r0,#0xb
000028 d3f8 BCC |L1.28|
;;;48 }
;;;49 }
00002a 4770 BX lr
ENDP
AREA ||i.NVIC_SCBDeInit||, CODE, READONLY, ALIGN=2
NVIC_SCBDeInit PROC
;;;62
;;;63 SCB->ICSR = 0x0A000000;
000000 490e LDR r1,|L2.60|
000002 f04ff04f MOV r2,#0xa000000
000006 2000 MOVS r0,#0
000008 600a STR r2,[r1,#0]
;;;64 SCB->VTOR = 0x00000000;
00000a 4602 MOV r2,r0
00000c 6048 STR r0,[r1,#4]
;;;65 SCB->AIRCR = AIRCR_VECTKEY_MASK;
00000e 4b0c LDR r3,|L2.64|
000010 608b STR r3,[r1,#8]
;;;66 SCB->SCR = 0x00000000;
000012 60c8 STR r0,[r1,#0xc]
;;;67 SCB->CCR = 0x00000000;
000014 6108 STR r0,[r1,#0x10]
000016 f6a1f6a1 SUB r1,r1,#0xd04
|L2.26|
;;;68 for(index = 0; index < 0x03; index++)
;;;69 {
;;;70 SCB->SHPR[index] = 0;
00001a eb01eb01 ADD r3,r1,r0,LSL #2
00001e f8c3f8c3 STR r2,[r3,#0xd18]
000022 1c40 ADDS r0,r0,#1
000024 2803 CMP r0,#3
000026 d3f8 BCC |L2.26|
000028 f601f601 ADD r1,r1,#0xd24
;;;71 }
;;;72 SCB->SHCSR = 0x00000000;
00002c 600a STR r2,[r1,#0]
;;;73 SCB->CFSR = 0xFFFFFFFF;
00002e f04ff04f MOV r0,#0xffffffff
000032 6048 STR r0,[r1,#4]
;;;74 SCB->HFSR = 0xFFFFFFFF;
000034 6088 STR r0,[r1,#8]
;;;75 SCB->DFSR = 0xFFFFFFFF;
000036 60c8 STR r0,[r1,#0xc]
;;;76 }
000038 4770 BX lr
ENDP
00003a 0000 DCW 0x0000
|L2.60|
00003c e000ed04 DCD 0xe000ed04
|L2.64|
000040 05fa0000 DCD 0x05fa0000
AREA ||i.NVIC_PriorityGroupConfig||, CODE, READONLY, ALIGN=2
NVIC_PriorityGroupConfig PROC
;;;102 /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
;;;103 SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
000000 4902 LDR r1,|L3.12|
000002 4308 ORRS r0,r0,r1
000004 4902 LDR r1,|L3.16|
000006 6008 STR r0,[r1,#0]
;;;104 }
000008 4770 BX lr
ENDP
00000a 0000 DCW 0x0000
|L3.12|
00000c 05fa0000 DCD 0x05fa0000
|L3.16|
000010 e000ed0c DCD 0xe000ed0c
AREA ||i.NVIC_Init||, CODE, READONLY, ALIGN=1
NVIC_Init PROC
;;;116 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
;;;117 {
000000 b5f0 PUSH {r4-r7,lr}
;;;118 u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
;;;119 u32 tmppre = 0, tmpsub = 0x0F;
000002 230f MOVS r3,#0xf
;;;120
;;;121 /* Check the parameters */
;;;122 assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
;;;123 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
;;;124 assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
;;;125 assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
;;;126
;;;127 if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
000004 78c2 LDRB r2,[r0,#3]
000006 7801 LDRB r1,[r0,#0]
000008 f04ff04f MOV r4,#0xe000e000
00000c 2701 MOVS r7,#1
00000e b342 CBZ r2,|L4.98|
;;;128 {
;;;129 /* Compute the Corresponding IRQ Priority --------------------------------*/
;;;130 tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
000010 f8d4f8d4 LDR r2,[r4,#0xd0c]
000014 f402f402 AND r2,r2,#0x700
000018 f5c2f5c2 RSB r2,r2,#0x700
00001c 0a12 LSRS r2,r2,#8
;;;131 tmppre = (0x4 - tmppriority);
00001e f1c2f1c2 RSB r5,r2,#4
;;;132 tmpsub = tmpsub >> tmppriority;
000022 40d3 LSRS r3,r3,r2
;;;133
;;;134 tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
000024 7842 LDRB r2,[r0,#1]
000026 40aa LSLS r2,r2,r5
;;;135 tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
000028 7885 LDRB r5,[r0,#2]
00002a 401d ANDS r5,r5,r3
00002c 4315 ORRS r5,r5,r2
;;;136
;;;137 tmppriority = tmppriority << 0x04;
;;;138 tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
00002e 078a LSLS r2,r1,#30
000030 012d LSLS r5,r5,#4
000032 0ed2 LSRS r2,r2,#27
000034 4095 LSLS r5,r5,r2
;;;139
;;;140 tmpreg = NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
000036 f021f021 BIC r1,r1,#3
00003a 190b ADDS r3,r1,r4
00003c f8d3f8d3 LDR r6,[r3,#0x400]
;;;141 tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
000040 21ff MOVS r1,#0xff
000042 4091 LSLS r1,r1,r2
;;;142 tmpreg &= ~tmpmask;
000044 438e BICS r6,r6,r1
;;;143 tmppriority &= tmpmask;
000046 400d ANDS r5,r5,r1
;;;144 tmpreg |= tmppriority;
000048 432e ORRS r6,r6,r5
;;;145
;;;146 NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
00004a f8c3f8c3 STR r6,[r3,#0x400]
;;;147
;;;148 /* Enable the Selected IRQ Channels --------------------------------------*/
;;;149 NVIC->ISER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
00004e 7800 LDRB r0,[r0,#0]
000050 f000f000 AND r1,r0,#0x1f
000054 408f LSLS r7,r7,r1
000056 0940 LSRS r0,r0,#5
000058 eb04eb04 ADD r0,r4,r0,LSL #2
00005c f8c0f8c0 STR r7,[r0,#0x100]
;;;150 (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
;;;151 }
;;;152 else
;;;153 {
;;;154 /* Disable the Selected IRQ Channels -------------------------------------*/
;;;155 NVIC->ICER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
;;;156 (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
;;;157 }
;;;158 }
000060 bdf0 POP {r4-r7,pc}
|L4.98|
000062 f001f001 AND r0,r1,#0x1f
000066 4087 LSLS r7,r7,r0
000068 0948 LSRS r0,r1,#5
00006a eb04eb04 ADD r0,r4,r0,LSL #2
00006e f8c0f8c0 STR r7,[r0,#0x180]
000072 bdf0 POP {r4-r7,pc}
ENDP
AREA ||i.NVIC_StructInit||, CODE, READONLY, ALIGN=1
NVIC_StructInit PROC
;;;170 /* NVIC_InitStruct members default value */
;;;171 NVIC_InitStruct->NVIC_IRQChannel = 0x00;
000000 2100 MOVS r1,#0
000002 7001 STRB r1,[r0,#0]
;;;172 NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
000004 7041 STRB r1,[r0,#1]
;;;173 NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
000006 7081 STRB r1,[r0,#2]
;;;174 NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
000008 70c1 STRB r1,[r0,#3]
;;;175 }
00000a 4770 BX lr
ENDP
AREA ||i.NVIC_SETPRIMASK||, CODE, READONLY, ALIGN=1
NVIC_SETPRIMASK PROC
;;;185 {
;;;186 __SETPRIMASK();
000000 f7fff7ff B.W __SETPRIMASK
;;;187 }
ENDP
AREA ||i.NVIC_RESETPRIMASK||, CODE, READONLY, ALIGN=1
NVIC_RESETPRIMASK PROC
;;;197 {
;;;198 __RESETPRIMASK();
000000 f7fff7ff B.W __RESETPRIMASK
;;;199 }
ENDP
AREA ||i.NVIC_SETFAULTMASK||, CODE, READONLY, ALIGN=1
NVIC_SETFAULTMASK PROC
;;;209 {
;;;210 __SETFAULTMASK();
000000 f7fff7ff B.W __SETFAULTMASK
;;;211 }
ENDP
AREA ||i.NVIC_RESETFAULTMASK||, CODE, READONLY, ALIGN=1
NVIC_RESETFAULTMASK PROC
;;;221 {
;;;222 __RESETFAULTMASK();
000000 f7fff7ff B.W __RESETFAULTMASK
;;;223 }
ENDP
AREA ||i.NVIC_BASEPRICONFIG||, CODE, READONLY, ALIGN=1
NVIC_BASEPRICONFIG PROC
;;;237
;;;238 __BASEPRICONFIG(NewPriority << 0x04);
000000 0100 LSLS r0,r0,#4
000002 f7fff7ff B.W __BASEPRICONFIG
;;;239 }
ENDP
AREA ||i.NVIC_GetBASEPRI||, CODE, READONLY, ALIGN=1
NVIC_GetBASEPRI PROC
;;;249 {
;;;250 return (__GetBASEPRI());
000000 f7fff7ff B.W __GetBASEPRI
;;;251 }
ENDP
AREA ||i.NVIC_GetCurrentPendingIRQChannel||, CODE, READONLY, ALIGN=2
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