📄 stm32f10x_nvic.txt
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NVIC_GetCurrentPendingIRQChannel PROC
;;;260 u16 NVIC_GetCurrentPendingIRQChannel(void)
;;;261 {
000000 4802 LDR r0,|L12.12|
;;;262 return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C));
000002 6800 LDR r0,[r0,#0]
000004 f3c0f3c0 UBFX r0,r0,#12,#10
;;;263 }
000008 4770 BX lr
ENDP
00000a 0000 DCW 0x0000
|L12.12|
00000c e000ed04 DCD 0xe000ed04
AREA ||i.NVIC_GetIRQChannelPendingBitStatus||, CODE, READONLY, ALIGN=1
NVIC_GetIRQChannelPendingBitStatus PROC
;;;273 ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)
;;;274 {
000000 4601 MOV r1,r0
;;;275 ITStatus pendingirqstatus = RESET;
;;;276 u32 tmp = 0x00;
;;;277
;;;278 /* Check the parameters */
;;;279 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;280
;;;281 tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
000002 f001f001 AND r3,r1,#0x1f
000006 2201 MOVS r2,#1
000008 409a LSLS r2,r2,r3
00000a 2000 MOVS r0,#0
;;;282
;;;283 if (((NVIC->ISPR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
00000c 0949 LSRS r1,r1,#5
00000e f04ff04f MOV r3,#0xe000e000
000012 eb03eb03 ADD r1,r3,r1,LSL #2
000016 f8d1f8d1 LDR r1,[r1,#0x200]
00001a 438a BICS r2,r2,r1
00001c d100 BNE |L13.32|
;;;284 {
;;;285 pendingirqstatus = SET;
00001e 2001 MOVS r0,#1
|L13.32|
;;;286 }
;;;287 else
;;;288 {
;;;289 pendingirqstatus = RESET;
;;;290 }
;;;291 return pendingirqstatus;
;;;292 }
000020 4770 BX lr
ENDP
AREA ||i.NVIC_SetIRQChannelPendingBit||, CODE, READONLY, ALIGN=2
NVIC_SetIRQChannelPendingBit PROC
;;;301 void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)
;;;302 {
000000 4901 LDR r1,|L14.8|
;;;303 /* Check the parameters */
;;;304 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;305
;;;306 *(u32*)0xE000EF00 = (u32)NVIC_IRQChannel;
;;;307 }
000002 6008 STR r0,[r1,#0]
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L14.8|
000008 e000ef00 DCD 0xe000ef00
AREA ||i.NVIC_ClearIRQChannelPendingBit||, CODE, READONLY, ALIGN=1
NVIC_ClearIRQChannelPendingBit PROC
;;;320
;;;321 NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
000000 f000f000 AND r2,r0,#0x1f
000004 2101 MOVS r1,#1
000006 4091 LSLS r1,r1,r2
000008 0940 LSRS r0,r0,#5
00000a f04ff04f MOV r2,#0xe000e000
00000e eb02eb02 ADD r0,r2,r0,LSL #2
000012 f8c0f8c0 STR r1,[r0,#0x280]
;;;322 }
000016 4770 BX lr
ENDP
AREA ||i.NVIC_GetCurrentActiveHandler||, CODE, READONLY, ALIGN=2
NVIC_GetCurrentActiveHandler PROC
;;;332 u16 NVIC_GetCurrentActiveHandler(void)
;;;333 {
000000 4802 LDR r0,|L16.12|
;;;334 return ((u16)(SCB->ICSR & (u32)0x3FF));
000002 6800 LDR r0,[r0,#0]
000004 f3c0f3c0 UBFX r0,r0,#0,#10
;;;335 }
000008 4770 BX lr
ENDP
00000a 0000 DCW 0x0000
|L16.12|
00000c e000ed04 DCD 0xe000ed04
AREA ||i.NVIC_GetIRQChannelActiveBitStatus||, CODE, READONLY, ALIGN=1
NVIC_GetIRQChannelActiveBitStatus PROC
;;;345 ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)
;;;346 {
000000 4601 MOV r1,r0
;;;347 ITStatus activeirqstatus = RESET;
;;;348 u32 tmp = 0x00;
;;;349
;;;350 /* Check the parameters */
;;;351 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;352
;;;353 tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
000002 f001f001 AND r3,r1,#0x1f
000006 2201 MOVS r2,#1
000008 409a LSLS r2,r2,r3
00000a 2000 MOVS r0,#0
;;;354
;;;355 if (((NVIC->IABR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
00000c 0949 LSRS r1,r1,#5
00000e f04ff04f MOV r3,#0xe000e000
000012 eb03eb03 ADD r1,r3,r1,LSL #2
000016 f8d1f8d1 LDR r1,[r1,#0x300]
00001a 438a BICS r2,r2,r1
00001c d100 BNE |L17.32|
;;;356 {
;;;357 activeirqstatus = SET;
00001e 2001 MOVS r0,#1
|L17.32|
;;;358 }
;;;359 else
;;;360 {
;;;361 activeirqstatus = RESET;
;;;362 }
;;;363 return activeirqstatus;
;;;364 }
000020 4770 BX lr
ENDP
AREA ||i.NVIC_GetCPUID||, CODE, READONLY, ALIGN=2
NVIC_GetCPUID PROC
;;;374 u32 NVIC_GetCPUID(void)
;;;375 {
000000 4801 LDR r0,|L18.8|
;;;376 return (SCB->CPUID);
000002 6800 LDR r0,[r0,#0]
;;;377 }
000004 4770 BX lr
ENDP
000006 0000 DCW 0x0000
|L18.8|
000008 e000ed00 DCD 0xe000ed00
AREA ||i.NVIC_SetVectorTable||, CODE, READONLY, ALIGN=2
NVIC_SetVectorTable PROC
;;;397
;;;398 SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80);
000000 4a02 LDR r2,|L19.12|
000002 4011 ANDS r1,r1,r2
000004 4301 ORRS r1,r1,r0
000006 4802 LDR r0,|L19.16|
000008 6001 STR r1,[r0,#0]
;;;399 }
00000a 4770 BX lr
ENDP
|L19.12|
00000c 1fffff80 DCD 0x1fffff80
|L19.16|
000010 e000ed08 DCD 0xe000ed08
AREA ||i.NVIC_GenerateSystemReset||, CODE, READONLY, ALIGN=2
NVIC_GenerateSystemReset PROC
;;;409 {
;;;410 SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04;
000000 4902 LDR r1,|L20.12|
000002 4801 LDR r0,|L20.8|
000004 6008 STR r0,[r1,#0]
;;;411 }
000006 4770 BX lr
ENDP
|L20.8|
000008 05fa0004 DCD 0x05fa0004
|L20.12|
00000c e000ed0c DCD 0xe000ed0c
AREA ||i.NVIC_GenerateCoreReset||, CODE, READONLY, ALIGN=2
NVIC_GenerateCoreReset PROC
;;;421 {
;;;422 SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01;
000000 4902 LDR r1,|L21.12|
000002 4801 LDR r0,|L21.8|
000004 6008 STR r0,[r1,#0]
;;;423 }
000006 4770 BX lr
ENDP
|L21.8|
000008 05fa0001 DCD 0x05fa0001
|L21.12|
00000c e000ed0c DCD 0xe000ed0c
AREA ||i.NVIC_SystemLPConfig||, CODE, READONLY, ALIGN=1
NVIC_SystemLPConfig PROC
;;;439 void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)
;;;440 {
000000 f04ff04f MOV r2,#0xe000e000
;;;441 /* Check the parameters */
;;;442 assert_param(IS_NVIC_LP(LowPowerMode));
;;;443 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;444
;;;445 if (NewState != DISABLE)
000004 2900 CMP r1,#0
;;;446 {
;;;447 SCB->SCR |= LowPowerMode;
000006 f8d2f8d2 LDR r1,[r2,#0xd10]
00000a d001 BEQ |L22.16|
00000c 4301 ORRS r1,r1,r0
00000e e000 B |L22.18|
|L22.16|
;;;448 }
;;;449 else
;;;450 {
;;;451 SCB->SCR &= (u32)(~(u32)LowPowerMode);
000010 4381 BICS r1,r1,r0
|L22.18|
000012 f8c2f8c2 STR r1,[r2,#0xd10]
;;;452 }
;;;453 }
000016 4770 BX lr
ENDP
AREA ||i.NVIC_SystemHandlerConfig||, CODE, READONLY, ALIGN=1
NVIC_SystemHandlerConfig PROC
;;;476
;;;477 tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F);
000000 f000f000 AND r2,r0,#0x1f
000004 2001 MOVS r0,#1
000006 4090 LSLS r0,r0,r2
000008 f04ff04f MOV r2,#0xe000e000
;;;478
;;;479 if (NewState != DISABLE)
00000c 2900 CMP r1,#0
;;;480 {
;;;481 SCB->SHCSR |= tmpreg;
00000e f8d2f8d2 LDR r1,[r2,#0xd24]
000012 d001 BEQ |L23.24|
000014 4301 ORRS r1,r1,r0
000016 e000 B |L23.26|
|L23.24|
;;;482 }
;;;483 else
;;;484 {
;;;485 SCB->SHCSR &= ~tmpreg;
000018 4381 BICS r1,r1,r0
|L23.26|
00001a f8c2f8c2 STR r1,[r2,#0xd24]
;;;486 }
;;;487 }
00001e 4770 BX lr
ENDP
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