masks8260.h

网口收发程序

/*------------------------------------------------------------------------*
*  FILE:  MASK8260.H                                                     
*                                                                        
*  DESCRIPTION:  Bit masks for PQ2 registers. Sequence of registers  
*                follows device memory map exactly.                      
*                                                                          
* HISTORY:
*
* 05 Nov 99  JAY
* 07 JAN 99  pdw        Updated to include mask registers/parameters for SCC Ethernet operation
*	                                       
*------------------------------------------------------------------------*/

/*------------------------------------------*
* CPM Command Register (CPCR)               *
*-------------------------------------------*
* NOTE: This register is cleared by reset.  *
*       See MPC8260 User's Manual.          *
*-------------------------------------------*/

#define CPCR_RST                 0x80000000  /* Software Reset Command */
#define CPCR_FLG                 0x00010000  /* Command Semaphore Flag */

/*-----------------------------------------------*/
/* Definitions for SCC CPCR Subblock/Page codes. */
/*-----------------------------------------------*/

#define  SCC1_PAGE_SUBBLOCK    0x00800000    /* page 0, code = 4 */
#define  SCC2_PAGE_SUBBLOCK    0x04A00000    /* page 1, code = 5 */
#define  SCC3_PAGE_SUBBLOCK    0x08C00000    /* page 2, code = 6 */
#define  SCC4_PAGE_SUBBLOCK    0x0CE00000    /* page 3, code = 7 */

/*-----------------------------*/
/* Opcode definitions for SCCs */
/*-----------------------------*/

#define CPCR_INIT_TX_RX_PARAMS   0x00000000   /* Opcode 0 */
#define CPCR_INIT_RX_PARAMS      0x00000001   /* Opcode 1 */
#define CPCR_INIT_TX_PARAMS      0x00000002   /* Opcode 2 */
#define CPCR_ENTER_HUNT_MODE     0x00000003   /* Opcode 3 */
#define CPCR_STOP_TX             0x00000004   /* Opcode 4 */
#define CPCR_GRACEFUL_STOP_TX    0x00000005   /* Opcode 5 */
#define CPCR_RESTART_TX          0x00000006   /* Opcode 6 */
#define CPCR_CLOSE_RX_BD         0x00000007   /* Opcode 7 */
#define CPCR_SET_GRP_ADDR        0x00000008   /* Opcode 8 */
#define CPCR_RESET_BCS           0x0000000A   /* Opcode 10 */

/*-----------------------------------------------------*/
/* General Definitions for SCC CPCR Command Operations */
/*-----------------------------------------------------*/

#define READY_TO_RX_CMD          0x00000000 

/*-------------------------*/
/* General SCC Definitions */
/*-------------------------*/

#define  DISABLE_TX_RX   0xFFFFFFCF  /* Clear the ENT/ENR bits in the GSMR
                                        Disables the transmit & Receive
                                        port                              */

#define  GSMR_L1_ENT  0x00000010      /* ENT bit for the GSMR low register */
#define  GSMR_L1_ENR  0x00000020      /* ENR bit for the GSMR low register */
#define  GSMR_L1_INT_LB  0x00000040   /* Internal Loopback mask */


#define  ALL_ONES    0xFFFFFFFF
#define  ALL_ZEROS   0x00000000


/************/
/* Ethernet */
/************/

/*--------------------------------*/
/* SCCE Register in Ethernet Mode */
/*--------------------------------*/

#define ENET_SCCE_GRA		0x0080   /* Graceful stop Complete */
#define ENET_SCCE_TXE		0x0010   /* Tx Error */
#define ENET_SCCE_RXF		0x0008   /* Rx Frame */
#define ENET_SCCE_BSY      0x0004 	/* Busy Condition */
#define ENET_SCCE_TXB		0x0002 	/* Tx Buffer */
#define ENET_SCCE_RXB      0x0001   /* Rx Buffer */


/*--------------------------------*/
/* SCCM Register in Ethernet Mode */
/*--------------------------------*/

#define ENET_SCCM_GRA	0x0080   /* Graceful stop Complete */
#define ENET_SCCM_TXE	0x0010   /* Tx Error */
#define ENET_SCCM_RXF	0x0008   /* Rx Frame */
#define ENET_SCCM_BSY   0x0004 	 /* Busy Condition */
#define ENET_SCCM_TXB	0x0002 	 /* Tx Buffer */
#define ENET_SCCM_RXB   0x0001   /* Rx Buffer */


/*--------------------------------*/
/* PSMR Register in Ethernet Mode */
/*--------------------------------*/

#define ENET_PSMR_HBC	0x8000   /* Heartbeat Checking */
#define ENET_PSMR_FC	0x4000   /* Force Collision */
#define ENET_PSMR_RSH	0x2000   /* Receive Short Frames */
#define ENET_PSMR_IAM	0x1000   /* Individual Address Mode */
#define ENET_PSMR_CRC   0x0C00   /* CRC Selection */
#define ENET_PSMR_PRO	0x0200   /* Promiscuous */
#define ENET_PSMR_BRO   0x0100   /* Broadcast Address */
#define ENET_PSMR_SBT   0x0080   /* Stop Backoff Timer */
#define ENET_PSMR_LPB	0x0040   /* Loopback Operation */
#define ENET_PSMR_SIP	0x0020   /* Sample Input Pins */ 
#define ENET_PSMR_LCW   0x0010   /* Late Collision Window */
#define ENET_PSMR_NIB   0x000E   /* Number of Ignored Bits */
#define ENET_PSMR_FDE   0x0001   /* Full Duplex Ethernet */