mpc8260.h

网口收发程序

   UWORD	ttemp;	    /* Tx temp */
  
   /* SMC UART-specific PRAM */
   UHWORD	max_idl;	/* Maximum IDLE Characters */
   UHWORD	idlc;		/* Temporary IDLE Counter */
   UHWORD	brkln;		/* Last Rx Break Length */
   UHWORD	brkec;		/* Rx Break Condition Counter */
   UHWORD	brkcr;		/* Break Count Register (Tx) */
   UHWORD	r_mask;		/* Temporary bit mask */
  
} _PackedType t_Smc_Pram;



/*---------------------------------------------------------------------------*/
/*						      IDMA PARAMETER RAM                             */
/*---------------------------------------------------------------------------*/

typedef  _Packed struct  
{
    UHWORD      ibase;       /* IDMA BD Base Address               */
    UHWORD      dcm;         /* DMA channel mode register          */
    UHWORD      ibdptr;      /* next bd ptr                        */
    UHWORD      DPR_buf;     /* ptr to internal 64 byte buffer     */
    UHWORD      BUF_inv;     /* The quantity of data in DPR_buf    */
    UHWORD      SS_max;      /* Steady State Max. transfer size    */
    UHWORD      DPR_in_ptr;  /* write ptr for the internal buffer  */
    UHWORD      sts;         /* Source Transfer Size               */
    UHWORD      DPR_out_ptr; /* read ptr for the internal buffer   */
    UHWORD      seob;        /* Source end of burst                */
    UHWORD      deob;        /* Destination end of burst           */
    UHWORD      dts;         /* Destination Transfer Size          */
    UHWORD      RetAdd;      /* return address when ERM==1         */
    UHWORD      Reserved;    /* reserved */
    UWORD       BD_cnt;      /* Internal byte count                */
    UWORD       S_ptr;       /* source internal data ptr           */
    UWORD       D_ptr;       /* destination internal data ptr      */
    UWORD       istate;      /* Internal state                     */

} _PackedType t_Idma_Pram;



/*-------------------------------------------------------------------*/
/*         INTER-INTEGRATED CIRCUIT  (I2C)	                     */
/*-------------------------------------------------------------------*/

typedef  _Packed struct 
{
   UHWORD	rbase;		/* RX BD base address */
   UHWORD	tbase;		/* TX BD base address */
   UBYTE	rfcr;		/* Rx function code */
   UBYTE	tfcr;		/* Tx function code */
   UHWORD	mrblr;		/* Rx buffer length */
   UWORD	rstate;		/* Rx internal state */
   UWORD	rptr;		/* Rx internal data pointer */
   UHWORD	rbptr;		/* rb BD Pointer */
   UHWORD	rcount;		/* Rx internal byte count */
   UWORD	rtemp;		/* Rx temp */
   UWORD	tstate;		/* Tx internal state */
   UWORD	tptr;		/* Tx internal data pointer */
   UHWORD	tbptr;		/* Tx BD pointer */
   UHWORD	tcount;		/* Tx byte count */
   UWORD	ttemp;		/* Tx temp */
} _PackedType t_I2c_Pram;



/*---------------------------------------------------------------------------*/
/*                       SERIAL PERIPHERAL INTERFACE  (SPI)                  */
/*---------------------------------------------------------------------------*/

typedef  _Packed struct  
{
   UHWORD	rbase;      /* Rx BD Base Address */
   UHWORD	tbase;      /* Tx BD Base Address */
   UBYTE    rfcr;       /* Rx function code */
   UBYTE    tfcr;       /* Tx function code */
   UHWORD	mrblr;      /* Rx buffer length */
   UWORD    rstate;     /* Rx internal state */
   UWORD    rptr;       /* Rx internal data pointer */
   UHWORD	rbptr;      /* Rx BD Pointer */
   UHWORD	rcount;     /* Rx internal byte count */
   UWORD    rtemp;      /* Rx temp */
   UWORD    tstate;     /* Tx internal state */
   UWORD    tptr;       /* Tx internal data pointer */
   UHWORD	tbptr;      /* Tx BD pointer */
   UHWORD	tcount;     /* Tx byte count */
   UWORD    ttemp;      /* Tx temp */
   UBYTE    reserved[8];
} _PackedType t_Spi_Pram;



/*---------------------------------------------------------------------------*/
/*   					RISC TIMER PARAMETER RAM                             */
/*---------------------------------------------------------------------------*/

typedef  _Packed struct  
{
 
   UHWORD	tm_base;    /* RISC timer table base adr */
   UHWORD	tm_ptr;     /* RISC timer table pointer */
   UHWORD	r_tmr;      /* RISC timer mode register */
   UHWORD	r_tmv;      /* RISC timer valid register */
   UWORD	tm_cmd;     /* RISC timer cmd register */
   UWORD	tm_cnt;     /* RISC timer internal cnt */
} _PackedType t_timer_pram;



/*--------------------------------------------------------------------------*/
/*                  ROM MICROCODE PARAMETER RAM AREA                        */
/*--------------------------------------------------------------------------*/

typedef  _Packed struct  
{
   UHWORD   rev_num;    /* Ucode Revision Number */
   UHWORD   d_ptr;      /* MISC Dump area pointer */
} _PackedType t_ucode_pram;








/*--------------------------------------------------------------------------*/
/*                MAIN DEFINITION OF INTERNAL MEMORY MAP                    */
/*--------------------------------------------------------------------------*/

typedef  _Packed struct 
{

/* cpm_ram */
    t_Mch_Pram    mch_pram[256]; /* MCC logical channels parameter ram */
    VUBYTE reserved0[0x4000];    /* Reserved area */
    
/* DPR_BASE+0x8000*/
    union 
    {
    
    /*for access to the PRAM structs for SCCs, FCCs, and MCCs */ 
       struct serials 
       {
           t_Scc_Pram scc_pram[4];
           t_Fcc_Pram fcc_pram[3];
           t_Mcc_Pram mcc_pram[2];
           VUBYTE reserved1[0x700];
       } serials;
        
    /* for access to ATM PRAM structs */
       struct atm
       {
           VUBYTE reserved2[0x400];
           t_Atm_Pram atm_pram[2];
           VUBYTE reserved3[0xa00];
       } atm;
        
    /* for access to the memory locations holding user-defined 
       base addresses of PRAM for SMCs, IDMA, SPI, and I2C. */     
       struct standard
       {
            VUBYTE scc1[0x100];
            VUBYTE scc2[0x100];
            VUBYTE scc3[0x100];
            VUBYTE scc4[0x100];
            VUBYTE fcc1[0x100];
            VUBYTE fcc2[0x100];
            VUBYTE fcc3[0x100];
            VUBYTE mcc1[0x80];
            VUBYTE reserved_0[0x7c];
            VUBYTE smc1[0x2];
            VUBYTE idma1[0x2];
            VUBYTE mcc2[0x80];
            VUBYTE reserved_1[0x7c];
            VUBYTE smc2[0x2];
            VUBYTE idma2[0x2];
            VUBYTE reserved_2[0xfc];
            VUBYTE spi[0x2];
            VUBYTE idma3[0x2];
            VUBYTE reserved_3[0xe0];
            VUBYTE timers[0x10];
            VUBYTE Rev_num[0x2];
            VUBYTE D_ptr[0x2];
            VUBYTE reserved_4[0x4];
            VUBYTE rand[0x4];
            VUBYTE i2c[0x2];
            VUBYTE idma4[0x2];
            VUBYTE reserved_5[0x500];
       } standard;
        
    } pram;
    
    VUBYTE reserved11[0x2000];      /* Reserved area */
    VUBYTE cpm_ram_dpram_2[0x1000]; /* Internal RAM */
    VUBYTE reserved12[0x4000];      /* Reserved area */

/* siu */
    VUWORD siu_siumcr;        /* SIU Module Configuration Register */
    VUWORD siu_sypcr;         /* System Protection Control Register */
    VUBYTE reserved13[0x6];   /* Reserved area */
    VUHWORD siu_swsr;         /* Software Service Register */

/* buses */
    VUBYTE reserved14[0x14];  /* Reserved area */
    VUWORD bcr;               /* Bus Configuration Register */
    VUBYTE ppc_acr;           /* Arbiter Configuration Register */
    VUBYTE reserved15[0x3];   /* Reserved area */
    VUWORD ppc_alrh;          /* Arbitration level Register (First clients)*/
    VUWORD ppc_alrl;          /* Arbitration Level Register (Next clients) */
    VUBYTE lcl_acr;           /* LCL Arbiter Configuration Register */
    VUBYTE reserved16[0x3];   /* Reserved area */
    VUWORD lcl_alrh;        /* LCL Arbitration level Register (First clients)*/
    VUWORD lcl_alrl;        /* LCL Arbitration Level Register (Next clients) */
    VUWORD tescr1;       /* PPC bus transfer error status control register 1 */
    VUWORD tescr2;       /* PPC bus transfer error status control register 2 */
    VUWORD ltescr1;    /* Local bus transfer error status control register 1 */
    VUWORD ltescr2;    /* Local bus transfer error status control register 2 */
    VUWORD pdtea;             /* PPC bus DMA Transfer Error Address */
    VUBYTE pdtem;             /* PPC bus DMA Transfer Error MSNUM  */
    VUBYTE reserved17[0x3];   /* Reserved area */
    VUWORD ldtea;             /* PPC bus DMA Transfer Error Address */
    VUBYTE ldtem;             /* PPC bus DMA Transfer Error MSNUM  */
    VUBYTE reserved18[0xa3];  /* Reserved area */

/* memc */
    struct mem_regs 
    {
        VUWORD memc_br;       /* Base Register */
        VUWORD memc_or;       /* Option Register */
    } mem_regs[12];
    VUBYTE reserved19[0x8];   /* Reserved area */
    VUWORD memc_mar;          /* Memory Address Register */
    VUBYTE reserved20[0x4];   /* Reserved area */
    VUWORD memc_mamr;         /* Machine A Mode Register */
    VUWORD memc_mbmr;         /* Machine B Mode Register */
    VUWORD memc_mcmr;         /* Machine C Mode Register */
    VUWORD memc_mdmr;         /* Machine D Mode Register */
    VUBYTE reserved21[0x4];   /* Reserved area */
    VUHWORD memc_mptpr;       /* Memory Periodic Timer Prescaler */
    VUBYTE reserved22[0x2];   /* Reserved area */
    VUWORD memc_mdr;          /* Memory Data Register */
    VUBYTE reserved23[0x4];   /* Reserved area */
    VUWORD memc_psdmr;        /* PowerPC Bus SDRAM machine Mode Register */
    VUWORD memc_lsdmr;        /* Local Bus SDRAM machine Mode Registe */
    VUBYTE memc_purt;         /* PowerPC Bus assigned UPM Refresh Timer */
    VUBYTE reserved24[0x3];   /* Reserved area */
    VUBYTE memc_psrt;         /* PowerPC BusBus assigned SDRAM Refresh Timer */
    VUBYTE reserved25[0x3];   /* Reserved area */
    VUBYTE memc_lurt;         /* Local Bus assigned UPM Refresh Timer */
    VUBYTE reserved26[0x3];   /* Reserved area */
    VUBYTE memc_lsrt;         /* Local Bus assigned SDRAM Refresh Timer */
    VUBYTE reserved27[0x3];   /* Reserved area */
    VUWORD memc_immr;         /* Internal Memory Map Register */

/* pci */
    VUWORD pcibr0;            /* Base address+valid for PCI window 1 */
    VUWORD pcibr1;            /* Base address+valid for PCI window 2 */
    VUBYTE reserved28[0x10];  /* Reserved area */
    VUWORD pcimsk0;           /* Mask for PCI window 1 */
    VUWORD pcimsk1;           /* Mask for PCI window 2 */
    VUBYTE reserved29[0x54];  /* Reserved area */

/* si_timers */
    VUHWORD si_timers_tmcntsc; /* Time Counter Status and Control Register */
    VUBYTE reserved30[0x2];    /* Reserved area */
    VUWORD si_timers_tmcnt;    /* Time Counter Register */
    VUWORD si_timers_tmcntsec; /* Time Counter Seconds*/
    VUWORD si_timers_tmcntal;  /* Time Counter Alarm Register */
    VUBYTE reserved31[0x10];   /* Reserved area */
    VUHWORD si_timers_piscr;   /* Periodic Interrupt Status and Control Reg. */
    VUBYTE reserved32[0x2];    /* Reserved area */
    VUWORD si_timers_pitc;     /* Periodic Interrupt Count Register */