📄 ethernet.c
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for (index = 12,pattern = 1; index < (TX_BUFFER_SIZE-4); index++,
pattern<<=1)
{
if (pattern == 0x0100)
pattern = 0x01;
TxBufferPool[4][index] = pattern;
}
/*-----------------------------------------*/
/* Buffer[5]: Load decreasing walking ones */
/*-----------------------------------------*/
for (index = 12,pattern = 0x80; index < (TX_BUFFER_SIZE-4); index++,
pattern>>=1)
{
if (pattern == 0x00)
pattern = 0x80;
TxBufferPool[5][index] = pattern;
}
/*--------------------------------------------*/
/* Buffer[6]: Load "Increment from 0" pattern */
/*--------------------------------------------*/
for (index = 12; index < (TX_BUFFER_SIZE-4); index++)
{
TxBufferPool[6][index] = index-2;
}
/*----------------------------------------------*/
/* Buffer[7]: Load "Decrement from 255" pattern */
/*----------------------------------------------*/
for (index = 12; index < (TX_BUFFER_SIZE-4); index++)
{
TxBufferPool[7][index] = (257-index);
}
/*-----------------------------------------------*/
/* Load destination addresses, source addresses, */
/* and type/length field into each Tx buffer */
/*-----------------------------------------------*/
bufcount = 0;
while (bufcount < 8)
{
TxBufferPool[bufcount][0] = 0x00;
TxBufferPool[bufcount][6] = 0x00;
TxBufferPool[bufcount][1] = 0x19;
TxBufferPool[bufcount][7] = 0x19;
TxBufferPool[bufcount][2] = 0x22;
TxBufferPool[bufcount][8] = 0x22;
TxBufferPool[bufcount][3] = 0x33;
TxBufferPool[bufcount][9] = 0x33;
TxBufferPool[bufcount][4] = 0x48;
TxBufferPool[bufcount][10] = 0x48;
TxBufferPool[bufcount][5] = 0x55;
TxBufferPool[bufcount][11] = 0x55;
TxBufferPool[bufcount][12] = 0x00;
TxBufferPool[bufcount][13] = 0xEE;
bufcount++;
}
} /* end of LoadTxBuffers */
/*------------------------------------------------------------------------
*
* FUNCTION NAME: InitParallelPorts
*
*
* DESCRIPTION:
*
* Sets up the parellel I/O pins to enable TXD/RXD for
* SCC1 on Port D
*
* EXTERNAL EFFECT:
*
* Initialised relevant PIO registers
* PARAMETERS: None
*
* RETURNS: None
*
*-----------------------------------------------------------------------*/
void InitParallelPorts()
{
/*------------------------------------------------------------*/
/* Configure the parallel ports so that TXD, RXD and BRGO for */
/* BRG1 are connected to the appropriate port pins and are */
/* configured according to their functions. */
/*------------------------------------------------------------*/
/*-------------------------------------------------*/
/* Clear the Port C and D Pin Assignment Registers */
/*-------------------------------------------------*/
IMM->io_regs[PORT_D].ppar = 0x00000000;
IMM->io_regs[PORT_C].ppar = 0x00000000;
/*-------------------------------------------------*/
/* Clear the Port C and D Data Direction Registers */
/*-------------------------------------------------*/
IMM->io_regs[PORT_D].pdir = 0x00000000;
IMM->io_regs[PORT_C].pdir = 0x00000000;
/*----------------------------------------------------*/
/* Program the Port C and D Special Options Registers */
/*----------------------------------------------------*/
IMM->io_regs[PORT_D].psor = 0x00000002;
IMM->io_regs[PORT_C].psor = 0x00000002;
/*---------------------------------------------------*/
/* Program the Port C and D Data Direction Registers */
/*---------------------------------------------------*/
IMM->io_regs[PORT_D].pdir = 0x00000002;
IMM->io_regs[PORT_C].pdir = 0x00000001;
/*-----------------------------------------------*/
/* Program the Port C and D Open-Drain Registers */
/*-----------------------------------------------*/
IMM->io_regs[PORT_D].podr = 0x00000000;
IMM->io_regs[PORT_C].podr = 0x00000000;
/*-----------------------------------------*/
/* Program the Port C and D Pin Assignment */
/* Registers RXD1 on PD31 and TXD1 on PD30 */
/* & brgo1 on PORT C */
/*-----------------------------------------*/
IMM->io_regs[PORT_D].ppar = 0x00000003;
IMM->io_regs[PORT_C].ppar = 0x00000001;
} /* end of InitParallelPorts */
/*------------------------------------------------------------------------
*
* FUNCTION NAME: InterruptControlInit
*
*
* DESCRIPTION:
*
* Initialises interrupt controller for enabling/masking interrupts
*
* EXTERNAL EFFECT:
*
* Interrupts enabled for SCC1 running Ethernet
*
* PARAMETERS: None
*
* RETURNS: None
*
*-----------------------------------------------------------------------*/
void InterruptControlInit()
{
/*---------------------------------------*/
/* Interrupt Handler for SCC1 Interrupts */
/*---------------------------------------*/
/*------------------------------------------------*/
/* Defult setting XSIU1 is the highest interrupt */
/* priority therefore no modications have been */
/* to the standard PQ2 interrupt priority order */
/*------------------------------------------------*/
IMM->ic_sicr = 0x0200;
/*-------------------------------------------------------------*/
/* Clear Pending Interrupts in SIU Interrupt Pending Register */
/* SIPNR by writing ones IPR */
/*-------------------------------------------------------------*/
IMM->ic_sipnr_h = ALL_ONES;
IMM->ic_sipnr_l = ALL_ONES;
/*-----------------------------------------------------*/
/* Note default values used for CPM Interrupt Priority */
/* Register SCPRR used */
/*-----------------------------------------------------*/
/*-----------------------------------------------*/
/* Set bits in SIU Interrupt Mask Register SIMR */
/* for SCC1 */
/*-----------------------------------------------*/
IMM->ic_simr_h = 0x00000000;
IMM->ic_simr_l = 0x00800000;
/*-----------------------------------------*/
/* Set SCCM for interrupts on RXF */
/*-----------------------------------------*/
IMM->scc_regs[SCC1].sccm = ENET_SCCM_RXF;
/*-----------------------------------------*/
/* Enable External Interrupts in the core */
/* by setting EE bit (bit 16) in the MSR */
/*-----------------------------------------*/
/* asm(" mfmsr r3 ");
asm(" ori r3,r3,0x8000 ");
asm(" mtmsr r3 "); /* using Diab syntax, Enable EE Bit in MSR */
asm(mfmsr r3);
asm(ori r3,r3,0x8000);
asm(mtmsr r3); /* using CodeWarrior syntax, Enable EE Bit in MSR */
} /* end of InterruptControlInit */
/*------------------------------------------------------------------------
*
* FUNCTION NAME: SCC1EtherInit
*
*
* DESCRIPTION:
*
* SCC1 Ethernet Initialization Routine.
*
* EXTERNAL EFFECT:
*
* Initialises clock configuration to generate a 2MHz clock on BRG1
* to be used for TX/RX on SCC1. It also initialise Parameter RAM and
* general purpose/protocol specific registers for Etherent operation.
* This function, when complete, will initiate or start the transfer of
* 8 Ethernet frames of data. For this simple example, each frame
* encompasses one BD of data.
*
* PARAMETERS: None
*
* RETURNS: None
*
*-----------------------------------------------------------------------*/
void SCC1EtherInit()
{
t_EnetScc_Pram* SCC1Ethernet;
/*--------------------------------------------------*/
/* Default division factor (Div by 8) for BRGCLK */
/*--------------------------------------------------*/
IMM->clocks_sccr &= 0xFFFFFFFC;
/*-----------------------------------------------------------------*/
/* Program Baud Rate Generator Configuration #1 Register (BRGC1). */
/* */
/* EN (Enable BRG Count) = 1 = Enable clocks to the BRG */
/* */
/* CD (Clock Divider) = 7 decimal = 7+1 */
/* */
/* The input frequency is 16.5Mhz Dividing it by 7 will give 2MHz. */
/* CD is programmed with 7 because the divider is CD+1 = 8 */
/* */
/* DIV16 (Divide-by-16) = 0 = divide by 1 */
/*-----------------------------------------------------------------*/
IMM->brgs_brgc1 = 0x0001000E;
/*----------------------------------------------------------------------*/
/* Initialise the CPM SCC Clock Route Register (CMXSCR) to connect SCC1 */
/* Tx and Rx clocks to BRG1. */
/* */
/* GR1 = 0 = SCC1 transmitter does not support the grant mechanism */
/* SC1 = 0 = SCC1 connected directly to the NMSI pins */
/* RS1CS = 000 = SCC1 receive clock is BRG1 */
/* TS1CS = 000 = SCC1 transmit clock is BRG1 */
/*----------------------------------------------------------------------*/
IMM->cpm_mux_cmxscr = 0x00000000;
/**************************************************/
/* Ethernet Specific Parameter RAM Initialization */
/**************************************************/
/*---------------------------------------------------*/
/* Setup Shortcut for defining Protocl Specific PRAM */
/*---------------------------------------------------*/
SCC1Ethernet = (t_EnetScc_Pram * ) &(IMM->pram.serials.scc_pram[SCC1].
SpecificProtocol.e);
SCC1Ethernet->c_pres = ENET_C_PRES; /* CRC Preset */
SCC1Ethernet->c_mask = ENET_C_MASK; /* Constant MASK for CRC */
SCC1Ethernet->crcec = ALL_ZEROS; /* CRC Error Counter */
SCC1Ethernet->alec = ALL_ZEROS; /* Align. Error Counter */
SCC1Ethernet->disfc = ALL_ZEROS; /* Discard Frame Counter */
SCC1Ethernet->pads = ENET_PAD; /* Short Frame PAD Char. */
SCC1Ethernet->ret_lim = ENET_RET_LIM; /* Retry Limit Threshold */
SCC1Ethernet->mflr = ENET_MFLR; /* Max Frame Length Reg. */
SCC1Ethernet->minflr = ENET_MINFLR; /* Min Frame Length Reg. */
SCC1Ethernet->maxd1 = ENET_MDMA; /* Max DMA1 Length Reg. */
SCC1Ethernet->maxd2 = ENET_MDMA; /* Max DMA2 Length Reg. */
SCC1Ethernet->gaddr1 = ALL_ZEROS; /* Group Addr. Filter 1 */
SCC1Ethernet->gaddr2 = ALL_ZEROS; /* Group Addr. Filter 2 */
SCC1Ethernet->gaddr3 = ALL_ZEROS; /* Group Addr. Filter 3 */
SCC1Ethernet->gaddr4 = ALL_ZEROS; /* Group Addr. Filter 4 */
SCC1Ethernet->paddr1_h = ENET_PADDR_H; /* Phys. Addr. 1 (MSB) */
SCC1Ethernet->paddr1_m = ENET_PADDR; /* Phys. Addr. 1 */
SCC1Ethernet->paddr1_l = ENET_PADDR_L /* Phys. Addr. 1 (LSB) */
SCC1Ethernet->p_per = ALL_ZEROS; /* Persistence */
SCC1Ethernet->iaddr1 = ALL_ZEROS; /* Ind. Addr. Filter 1 */
SCC1Ethernet->iaddr2 = ALL_ZEROS; /* Ind. Addr. Filter 2 */
SCC1Ethernet->iaddr3 = ALL_ZEROS; /* Ind. Addr. Filter 3 */
SCC1Ethernet->iaddr4 = ALL_ZEROS; /* Ind. Addr. Filter 4 */
SCC1Ethernet->taddr_h = ALL_ZEROS; /* Temp Address (MSB) */
SCC1Ethernet->taddr_m = ALL_ZEROS; /* Temp Address */
SCC1Ethernet->taddr_l = ALL_ZEROS; /* Temp Address (LSB) */
/********************************************************/
/* Common To All Protocols Parameter RAM Initialization */
/********************************************************/
/*---------------------------------*/
/* Set RXBD tbl start at Dual Port */
/*---------------------------------*/
IMM->pram.serials.scc_pram[SCC1].rbase = (UHWORD)&RxTxBD->RxBD[0];
/*---------------------------------*/
/* Set TXBD tbl start at Dual Port */
/*---------------------------------*/
IMM->pram.serials.scc_pram[SCC1].tbase = (UHWORD)&RxTxBD->TxBD[0];
/*-------------------------------------------*/
/* Set RFCR,TFCR -- Rx,Tx Function Code */
/* GBL= 0 = Snooping Disabled */
/* BO = 10 = PowerPC Little-Endian */
/* TC[2] = 0 Transfer Code */
/* DTB = 0 = 60x bus used for SDMA Operation */
/*-------------------------------------------*/
IMM->pram.serials.scc_pram[SCC1].rfcr = 0x10;
IMM->pram.serials.scc_pram[SCC1].tfcr = 0x10;
/*-----------------------------------------*/
/* Set MRBLR -- Max. Receive Buffer Length */
/* (Must be a multiple of 4, so use 1520) */
/*-----------------------------------------*/
IMM->pram.serials.scc_pram[SCC1].mrblr = ENET_MRBLR;
/****************************/
/* Register Initializations */
/****************************/
/*-----------------------------------------------------*/
/* Initialize GSMR_H 32Bit Default Setting */
/*-----------------------------------------------------*/
IMM->scc_regs[SCC1].gsmr_h = 0;
/*-------------------------------------------------------*/
/* Initialize GSMR_L: */
/* */
/* EDGE=00, TCI=1, TSNC=10, RINV=0, TINV=0, TPL=100, */
/* TPP=01, TEND=0, TDCR/RDCR=00, RNC/TENC=000, DIAG = 01 */
/* ENR/ENT=0, MODE = 1100 */
/*-------------------------------------------------------*/
IMM->scc_regs[SCC1].gsmr_l = 0x1088004C;
/*-------------------*/
/* Set DSR to 0xD555 */
/*-------------------*/
IMM->scc_regs[SCC1].dsr = ENET_DSR;
/*------------------------------------------------*/
/* Initialize PSMR: */
/* */
/* HBC=0, FC=0, RSH=0, IAM=0, CRC=10, PRO=0, */
/* BRO=0, SBT=0, LPB=1, LCW=0, NIB = 101, FDE=0 */
/*------------------------------------------------*/
IMM->scc_regs[SCC1].psmr = 0x084A;
/*-----------------------------------------*/
/* Clear SCCE Register by writing all 1's. */
/*-----------------------------------------*/
IMM->scc_regs[SCC1].scce = 0xFFFF;
/*-----------------------------------------------------------------*/
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