pq27e_init.cfg

网口收发程序

#######################################
#FILE
#	$RCSfile: PQ27e_init.cfg,v $
#	$Date: 2003/11/03 10:10:35 $
#	$Revision: 1.3 $
#DESCRIPTION
#
# Initialization file for
# the Motorola MPC8272 ADS target
#
#COPYRIGHT	
#	(c) 2003 Metrowerks Corporation
#	All rights reserved.
#HISTORY
#   $Log: PQ27e_init.cfg,v $
#   Revision 1.3  2003/11/03 10:10:35  milies
#   added configuration for Security Co-Processor internal memory space
#   
########################################

# IMMR assumed to be at 0x0f000000 due to hw config word

# Set the IMMR so the debugger plugin knows where it is since
# the IMMR itself is a memory mapped register. This does not
# actually write anything to the target, it is simply to inform
# the debugger plugin where the IMMR is, writing SPR311 (MBAR) register

#setMMRBaseAddr 0x0f000000
writereg	MBAR	0x0f000000

# SYPCR: turn off watchdog timer
writemmr	SYPCR		0xffffffc3

writemmr	IMMR	0x04700000

#setMMRBaseAddr 0x04700000
writereg	MBAR	0x04700000

writemmr	SCCR	0x00000001

writemmr	RMR			0x0001		# RMR=1: Set checkstop reset enable in the Reset Mode Register
writemmr	MPTPR		0x2800		# MPTPR: Set the Memory Periodic Timer Prescaler

# CS0 is flash at 0xff800000, 32-bit port, no error checking, writable, GPCM, 60x bus, valid

writemmr	BR0		0xff801801
writemmr	OR0		0xff800876


# CS1 is board control & status registers at 0x04500000 

writemmr	BR1		0x04501801
writemmr	OR1		0xffff8010


# CS2 is SDRAM, 64-bit port at 0x00000000

writemmr	OR2		0xfc002ec0
writemmr	BR2		0x00000041

writemmr	PSRT		0x13
writemmr	MPTPR		0x2800
# precharge all banks
writemmr	PSDMR		0x824b36a3
writemmr	PSDMR		0xaa4b36a3 
# perform an access
writemem.b	0x00000000	0x00
# cbr refresh
writemmr	PSDMR		0x8a4b36a3
# perform 8 accesses
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
; Issue Mode register write
writemmr	PSDMR		0x9a4b36a3
writemem.b	0x00000190	0x00
writemmr	PSDMR		0xc24b36a3

writemmr	TESCR1	0x00004000 
writemmr	TESCR2	0x00000000 

writemmr	LSRT		0

# PCI init
writemmr	OR3		0xFFFF8010
writemmr	BR3		0x04731801

#writemmr	LURT		0x00


# PCI registers
writemem.l 	0x04710880 	0x01000000 #PCI_GCR PCI General Control Register

writemem.l 	0x047101c4 	0xff800000 #PCIMSK0
writemem.l 	0x047101ac 	0x04800001 #PCIBR0
writemem.l 	0x047101c8 	0xc0000000 #PCIMSK1
writemem.l 	0x047101b0 	0x80000001 #PCIBR1


writemmr 	PPC_ALRH 	0x30126754
writemmr 	PPC_ACR 	0x03


# SEC configuration

# program SEC Mask Register with value 0xFFFE0000 - 128 KB memory space
writemem.l	0x047101BC	0xFFFE0000 #SECMR
# program SEC Base Register - IMMR + 0x40000
writemem.l	0x047101B4	0x04740001 #SECBR



# The MSR comes up with a value of 0x40, which means the exception prefix
# is 0xfff00000.  The trap exception fails to execute properly so we can
# setup breakpoints unless MSR[IP] = 0.
writereg	MSR		0x00003002