📄 readwriteflash.lst
字号:
00C5 +1 179 STA BIT SMB0CN.5 ; START FLAG
00C6 +1 180 TXMODE BIT SMB0CN.6 ; TRANSMIT MODE INDICATOR
00C7 +1 181 MASTER BIT SMB0CN.7 ; MASTER/SLAVE INDICATOR
+1 182
+1 183 ; TMR2CN 0xC8
00C8 +1 184 T2XCLK BIT TMR2CN.0 ; TIMER 2 EXTERNAL CLOCK SELECT
00CA +1 185 TR2 BIT TMR2CN.2 ; TIMER 2 ON/OFF CONTROL
00CB +1 186 T2SPLIT BIT TMR2CN.3 ; TIMER 2 SPLIT MODE ENABLE
00CD +1 187 TF2LEN BIT TMR2CN.5 ; TIMER 2 LOW BYTE INTERRUPT ENABLE
00CE +1 188 TF2L BIT TMR2CN.6 ; TIMER 2 LOW BYTE OVERFLOW FLAG
00CF +1 189 TF2H BIT TMR2CN.7 ; TIMER 2 HIGH BYTE OVERFLOW FLAG
+1 190
A51 MACRO ASSEMBLER READWRITEFLASH 11/09/2008 15:13:43 PAGE 4
+1 191 ; PSW 0xD0
00D0 +1 192 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG
00D1 +1 193 F1 BIT PSW.1 ; USER FLAG 1
00D2 +1 194 OV BIT PSW.2 ; OVERFLOW FLAG
00D3 +1 195 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0
00D4 +1 196 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1
00D5 +1 197 F0 BIT PSW.5 ; USER FLAG 0
00D6 +1 198 AC BIT PSW.6 ; AUXILIARY CARRY FLAG
00D7 +1 199 CY BIT PSW.7 ; CARRY FLAG
+1 200
+1 201 ; PCA0CN 0xD8H
00D8 +1 202 CCF0 BIT PCA0CN.0 ; PCA0 MODULE 0 CAPTURE/COMPARE FLAG
00D9 +1 203 CCF1 BIT PCA0CN.1 ; PCA0 MODULE 1 CAPTURE/COMPARE FLAG
00DA +1 204 CCF2 BIT PCA0CN.2 ; PCA0 MODULE 2 CAPTURE/COMPARE FLAG
00DB +1 205 CCF3 BIT PCA0CN.3 ; PCA0 MODULE 3 CAPTURE/COMPARE FLAG
00DC +1 206 CCF4 BIT PCA0CN.4 ; PCA0 MODULE 4 CAPTURE/COMPARE FLAG
00DE +1 207 CR BIT PCA0CN.6 ; PCA0 COUNTER RUN CONTROL
00DF +1 208 CF BIT PCA0CN.7 ; PCA0 COUNTER OVERFLOW FLAG
+1 209
+1 210 ; ADC0CN 0xE8H
00E8 +1 211 AD0CM0 BIT ADC0CN.0 ; ADC0 CONVERSION MODE SELECT 0
00E9 +1 212 AD0CM1 BIT ADC0CN.1 ; ADC0 CONVERSION MODE SELECT 1
00EA +1 213 AD0CM2 BIT ADC0CN.2 ; ADC0 CONVERSION MODE SELECT 2
00EB +1 214 AD0WINT BIT ADC0CN.3 ; ADC0 WINDOW COMPARE INTERRUPT FLAG
00EC +1 215 AD0BUSY BIT ADC0CN.4 ; ADC0 BUSY FLAG
00ED +1 216 AD0INT BIT ADC0CN.5 ; ADC0 CONVERISION COMPLETE INTERRUPT FLAG
00EE +1 217 AD0TM BIT ADC0CN.6 ; ADC0 TRACK MODE
00EF +1 218 AD0EN BIT ADC0CN.7 ; ADC0 ENABLE
+1 219
+1 220 ; SPI0CN 0xF8H
00FF +1 221 SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG
00FE +1 222 WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
00FD +1 223 MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG
00FC +1 224 RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
00FB +1 225 NSSMD1 BIT SPI0CN.3 ; SPI 0 SLAVE SELECT MODE 1
00FA +1 226 NSSMD0 BIT SPI0CN.2 ; SPI 0 SLAVE SELECT MODE 0
00F9 +1 227 TXBMT BIT SPI0CN.1 ; SPI 0 TRANSMIT BUFFER EMPTY
00F8 +1 228 SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE
229
0000 230 org 00h
0000 0200B3 231 LJMP Config
00B3 232 org 0B3h ; End of Interrupt Vector space.
00B3 233 Config:
00B3 75E101 234 mov XBR0, #001h ; Crossbar Register 1
00B6 75E2C0 235 mov XBR1, #0C0h ; Crossbar Register 2
00B9 53D9BF 236 ANL PCA0MD, #NOT(040h) ; clear Watchdog Enable bit
00BC 75A684 237 mov P2MDOUT, #10000100B ; Output configuration for P2
00BF 75B283 238 mov OSCICN, #083h ; Internal Oscillator Control Register
239
00C2 240 main2:
241
00C2 7800 242 MOV R0,#00H
00C4 7900 243 MOV R1,#00H
00C6 900300 244 MOV DPTR,#0300H
00C9 7400 245 MOV A,#00H
00CB 93 246 MOVC A,@A+DPTR
00CC F8 247 MOV R0,A
00CD 900301 248 MOV DPTR,#0301H
00D0 7400 249 MOV A,#00H
00D2 93 250 MOVC A,@A+DPTR
00D3 F9 251 MOV R1,A
252
00D4 D2A2 253 SETB P2.2
00D6 D2A7 254 SETB P2.7
00D8 C2A2 255 CLR P2.2
00DA C2A7 256 CLR P2.7
A51 MACRO ASSEMBLER READWRITEFLASH 11/09/2008 15:13:43 PAGE 5
257
258
00DC C2AF 259 CLR EA
260
00DE 261 WR:
00DE 7800 262 MOV R0,#00H
00E0 7900 263 MOV R1,#00H
00E2 D2A7 264 SETB P2.7
00E4 D2A2 265 SETB P2.2
266
00E6 267 READ01:
00E6 900300 268 MOV DPTR,#0300H
00E9 7400 269 MOV A,#00H
00EB 93 270 MOVC A,@A+DPTR
00EC 12014E 271 lcall delay25ms
00EF F8 272 MOV R0,A
273
00F0 6401 274 XRL A,#01H
00F2 6007 275 JZ P01
00F4 D2A2 276 SETB P2.2
00F6 D2A7 277 SETB P2.7
00F8 0200FD 278 LJMP READ02
279
00FB C2A2 280 P01: CLR P2.2
281
00FD 282 READ02:
00FD 900301 283 MOV DPTR,#0301H
0100 7400 284 MOV A,#00H
0102 93 285 MOVC A,@A+DPTR
0103 12014E 286 lcall delay25ms
287
0106 F9 288 MOV R1,A
289
0107 6402 290 XRL A,#02H
0109 603F 291 JZ P02
010B D2A2 292 SETB P2.2
010D D2A7 293 SETB P2.7
294
010F 75B680 295 MOV FLSCL,#10000000B
0112 C2AF 296 CLR EA
0114 438F02 297 ORL PSCTL,#00000010B
0117 438F01 298 ORL PSCTL,#00000001B
011A 75B7A5 299 MOV FLKEY,#0xA5
011D 75B7F1 300 MOV FLKEY,#0xF1
0120 900300 301 MOV DPTR,#0300H
0123 7401 302 MOV A,#01H
0125 F0 303 MOVX @DPTR,A
0126 538FFD 304 ANL PSCTL,#11111101B
305
0129 75B7A5 306 MOV FLKEY,#0xA5
012C 75B7F1 307 MOV FLKEY,#0xF1
012F 900300 308 MOV DPTR,#0300H
0132 7401 309 MOV A,#01H
0134 F0 310 MOVX @DPTR,A
0135 75B7A5 311 MOV FLKEY,#0xA5
0138 75B7F1 312 MOV FLKEY,#0xF1
013B 900301 313 MOV DPTR,#0301H
013E 7402 314 MOV A,#02H
0140 F0 315 MOVX @DPTR,A
0141 538FFE 316 ANL PSCTL,#11111110B
0144 D2A2 317 setb P2.2
0146 D2A7 318 SETB P2.7
0148 2148 319 ajmp $
320
014A 321 P02:
014A C2A7 322 CLR P2.7
A51 MACRO ASSEMBLER READWRITEFLASH 11/09/2008 15:13:43 PAGE 6
323
014C 214C 324 AJMP $
325
014E 7B05 326 delay25ms: mov r3, #05
;2
0150 79C8 327 delay25msa: mov r1, #200 ;2
0152 7AA4 328 delay25msb: mov r2, #164 ;2
0154 DAFE 329 djnz r2, $ ;2/
3 2+164*3+2=496
0156 00 330 nop
;1 496+1=497
0157 D9F9 331 djnz r1, delay25msb ;2/
3 2+(497+3)*200+2=100004
0159 DBF5 332 djnz r3, delay25msa
;2/3 2+()*5+2=500024
015B 22 333 ret
;1 500025 ;;;need 20MHz
334
335
336
337
338
339 END
A51 MACRO ASSEMBLER READWRITEFLASH 11/09/2008 15:13:43 PAGE 7
XREF SYMBOL TABLE LISTING
---- ------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES / REFERENCES
AC . . . . . . . . B ADDR 00D0H.6 A 198#
ACC. . . . . . . . D ADDR 00E0H A 104#
ACK. . . . . . . . B ADDR 00C0H.1 A 175#
ACKRQ. . . . . . . B ADDR 00C0H.3 A 177#
AD0BUSY. . . . . . B ADDR 00E8H.4 A 215#
AD0CM0 . . . . . . B ADDR 00E8H.0 A 211#
AD0CM1 . . . . . . B ADDR 00E8H.1 A 212#
AD0CM2 . . . . . . B ADDR 00E8H.2 A 213#
AD0EN. . . . . . . B ADDR 00E8H.7 A 218#
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