tx.h

来自「ixp2400的一个小程序」· C头文件 代码 · 共 120 行

//  Copyright (C) 2002-2003 Intel Corporation, All Rights Reserved.
//  Permission is hereby granted to merge this program code with 
//  other program material to create a derivative work.  This 
//  derivative work may be distributed in compiled object form only.
//  Any other publication of this program, in any form, without the 
//  explicit permission of the copyright holder is prohibited.
//
//  Send questions and comments to [e-mail], 
//  [e-mail]

//-------------------------------------------------------------------
// tx.h - Chapter 5
// Common values and datastructures for the transmit segmentation
// task
//

#ifndef TX_H
#define TX_H


//-------------------------------------------------------------------
// Bit positions within the MSF transmit control CSR
/*#define TX_EN_SPHY_BITPOS					29
Transmit Enable for SPI-4.
0—Do not transmit TBUF elements from SPI-4
partition. The effect is the same as if no SPI-4 TBUF
element is valid.
1—Transmit valid SPI-4 TBUF elements as defined in
this spec.
Whenever TX_EN_SS is cleared, the TX_FLUSH bits of the
used partitions must be set to reset the partition before
resetting TX_EN_SS re-enable the partition.*/
/*#define TX_ENABLE_BITPOS					10
Enables transmission.
0—All Transmit output signals remain driven low.
1—Normal transmit operation is enabled.
Note this bit does not control TCLK. TCLK is controlled by
MSF_CLK_CONTROL[TCLK_EN].*/
/*#define TBUF_ELE_SIZE_0_BITPOS				2
Indicates element size for partition 0 of TBUF. Number of
elements is a function of number of partitions—see
Table 5-45.
00—64 bytes
01—128 bytes
10—256 bytes
11—Reserved*/
/*#define TBUF_PARTITION_BITPOS				0
Controls the number of partitions for TBUF elements.
00–1 way—All elements allocated from
TBUF_Element_Freelist_0.
01–2 way—? of elements allocated from
TBUF_Element_Freelist_0 and ? from
TBUF_Element_Freelist_1.
10–3 way—1/2 of elements allocated from
TBUF_Element_Freelist_0, 3/8 from
TBUF_Element_Freelist_1, and 1/8 from
TBUF_Element_Freelist_2.
11—Reserved*/
// the mst_tx_control bitpos for spi3
#define TX_EN_SPHY_BITPOS       28 
#define TBUF_ELE_SIZE_0_BITPOS  2
#define TX_MPHY_LEVEL2          14
#define TX_MPHY_EN              19
#define TX_MPHY_MODE            18
#define TX_WIDTH                20
#define TX_MPHY_POLL_MODE       17
#define TX_MODE 				22

//-------------------------------------------------------------------
// MSF memory map
#define MSF_TX_CONTROL_ADDR					0x4
#define MSF_TX_SEQUENCE_0_ADDR				0x60
#define MSF_TBUF_CONTROL_BASE_ADDR			0x1800
#define MSF_TBUF_BASE_ADDR					0x2000
//--------add the tx_up_control address
 
#define MSF_TX_UP_CONTROL_0_ADDR	     0x0090
#define MSF_TX_UP_CONTROL_1_ADDR	     0x0094
#define MSF_TX_UP_CONTROL_2_ADDR	     0x0098
#define MSF_TX_UP_CONTROL_3_ADDR	     0x009c

//-----------
#define TX_UP_CONTROL_CPMODE            4
#define TX_UP_CONTROL_PPMODE			5
#define TX_UP_CONTROL_DRTIME            0

// MicroC data structures
#ifdef MICRO_C

//-------------------------------------------------------------------
// The SPI4 tbuf control words
//modify by rock, the pos-phy transimit control word formate
typedef struct s_spi4_tcw  
{
	union
	{
		struct
		{
			unsigned int payload_length : 8,
						 prepend_offset : 3,
						 prepend_length : 5,
						 payload_offset : 3,
						 res1			: 1,
						 skip			: 1,
						 err			: 1,
						 sop			: 1,
						 eop 			: 1,
						 m32ci			: 1,
						 res2			: 2,
						 channel		: 5;
						 
		} parts;
		unsigned int whole;
	} control_word;
	unsigned int reserved;
} spi4_tcw_t;

#endif // MICRO_C

#endif //TX_H