spi4_rx_dl_uc.list

ixp2400的一个小程序

sram_atomic 0 37;
sram_enqueue 0 43;
sram_dequeue 0 46;
scratch_rw 0 18;
scratch_ring 0 18;
sram_rd_qdesc 0 18;
sram_journal 0 18;
cap_rw 0 18;
msf_rw 0 18;
reflect_rw 0 18;
hash 0 63;
dram_rbuf_tbuf 0 53;
scratch_atomic 0 24;
sram_csr_rw 0 24;
cap_csr_rw 0 24;
value 0 14;
}
.%type E4 {
local_csr_ustore_address 0;
local_csr_ustore_data_lower 1;
local_csr_ustore_data_upper 2;
local_csr_ustore_error_status 3;
local_csr_alu_out 4;
local_csr_ctx_arb_cntl 5;
local_csr_ctx_enables 6;
local_csr_cc_enable 7;
local_csr_csr_ctx_pointer 8;
local_csr_indirect_ctx_sts 16;
local_csr_active_ctx_sts 17;
local_csr_indirect_ctx_sig_events 18;
local_csr_active_ctx_sig_events 19;
local_csr_indirect_ctx_wakeup_events 20;
local_csr_active_ctx_wakeup_events 21;
local_csr_indirect_ctx_future_count 22;
local_csr_active_ctx_future_count 23;
local_csr_byte_index 28;
local_csr_indirect_lm_addr_0 24;
local_csr_active_lm_addr_0 25;
local_csr_indirect_lm_addr_1 26;
local_csr_active_lm_addr_1 27;
local_csr_indirect_lm_addr_0_byte_index 56;
local_csr_active_lm_addr_0_byte_index 57;
local_csr_indirect_lm_addr_1_byte_index 58;
local_csr_active_lm_addr_1_byte_index 59;
local_csr_t_index_byte_index 61;
local_csr_t_index 29;
local_csr_indirect_future_count_signal 30;
local_csr_active_future_count_signal 31;
local_csr_nn_put 32;
local_csr_nn_get 33;
local_csr_timestamp_low 48;
local_csr_timestamp_high 49;
local_csr_next_neighbor_signal 64;
local_csr_prev_neighbor_signal 65;
local_csr_same_me_signal 66;
local_csr_crc_remainder 80;
local_csr_profile_count 81;
local_csr_pseudo_random_number 82;
local_csr_datapath_signature 83;
local_csr_datapath_signature_enable 84;
local_csr_debug 85;
local_csr_local_csr_status 96;
local_csr_reserved 255;
}
.%type E4 {
bytes_0_3 0;
bytes_0_2 1;
bytes_0_1 2;
byte_0 3;
bytes_1_3 4;
bytes_2_3 5;
byte_3 6;
}
.%type S4 cam_lookup_t{
__unnamed 0 72;
}
.%type S4 {
__unnamed 0 73;
value 0 14;
}
.%type S4 {
zeros1 0:12:20 14;
state 0:8:4 14;
hit 0:7:1 14;
entry_num 0:3:4 14;
zeros2 0:0:3 14;
}
.%type I8
.%type E4 {
kill 0;
voluntary 1;
bpt 2;
}
.%type E4 {
inp_state_nn_empty 0;
inp_state_nn_full 1;
inp_state_scr_ring0_status 2;
inp_state_scr_ring1_status 3;
inp_state_scr_ring2_status 4;
inp_state_scr_ring3_status 5;
inp_state_scr_ring4_status 6;
inp_state_scr_ring5_status 7;
inp_state_scr_ring6_status 8;
inp_state_scr_ring7_status 9;
inp_state_scr_ring8_status 10;
inp_state_scr_ring9_status 11;
inp_state_scr_ring10_status 12;
inp_state_scr_ring11_status 13;
inp_state_scr_ring0_full 2;
inp_state_scr_ring1_full 3;
inp_state_scr_ring2_full 4;
inp_state_scr_ring3_full 5;
inp_state_scr_ring4_full 6;
inp_state_scr_ring5_full 7;
inp_state_scr_ring6_full 8;
inp_state_scr_ring7_full 9;
inp_state_scr_ring8_full 10;
inp_state_scr_ring9_full 11;
inp_state_scr_ring10_full 12;
inp_state_scr_ring11_full 13;
inp_state_fci_not_empty 14;
inp_state_fci_full 15;
inp_state_fcififo_empty 14;
inp_state_fcififo_full 15;
}
.%type U4
.%type I4
.%type P2 80
.%type S16 ring_data_t{
handle 0 81;
length 4 77;
offset 8 77;
sequence 12 77;
}
.%type S4 {
__unnamed 0 82;
}
.%type S4 {
__unnamed 0 83;
value 0 77;
}
.%type S4 {
eop 0:31:1 77;
sop 0:30:1 77;
seg_count 0:24:6 77;
lw_offset 0:0:24 77;
}
.%type P1 85
.%type U4
.%type P2 87
.%type S4 {
__unnamed 0 88;
}
.%type S4 {
__unnamed 0 89;
value 0 90;
}
.%type S4 {
eop 0:31:1 90;
sop 0:30:1 90;
seg_count 0:24:6 90;
lw_offset 0:0:24 90;
}
.%type U4
.%type E4 {
POOL0 0;
POOL1 1;
POOL2 2;
POOL3 3;
POOL4 4;
POOL5 5;
POOL6 6;
POOL7 7;
}
.%type P2 93
.%type I4
.%type S32 {
__unnamed 0 95;
value 0 97;
}
.%type S32 {
bufferNext 0 87;
bufferSize 4 96;
offset 6 96;
packetSize 8:16:16 90;
freeListId 8:12:4 90;
rxStat 8:8:4 90;
headerType 8:0:8 90;
inputPort 12 96;
outputPort 14 96;
nextHopId 16:16:16 90;
fabricPort 16:8:8 90;
reserved 16:4:4 90;
nhidType 16:0:4 90;
colorId 20:28:4 90;
reserved1 20:24:4 90;
flowId 20:0:24 90;
classId 24 96;
reserved2 26 96;
packetNext 28 90;
}
.%type U2
.%type A32 90
.%type P2 87
.%type P2 100
.%type U4
.%type S8 s_spi4_rsw{
w1 0 102;
w2 4 104;
}
.%type S4 {
parts 0 103;
whole 0 90;
}
.%type S4 {
rprot 0:31:1 90;
element 0:24:7 90;
byte_count 0:16:8 90;
sop 0:15:1 90;
eop 0:14:1 90;
err 0:13:1 90;
len_err 0:12:1 90;
par_err 0:11:1 90;
abort_err 0:10:1 90;
null 0:9:1 90;
type 0:8:1 90;
addr 0:0:8 90;
}
.%type S4 {
whole 0 90;
}
.%type S4 {
parts 0 106;
whole 0 90;
}
.%type S4 {
res 0:16:16 90;
sig_no 0:12:4 90;
me_no 0:7:5 90;
thd 0:4:3 90;
xfer_reg 0:0:4 90;
}
.%type P3 100
.%type P2 109
.%type S8 {
even 0 93;
odd 4 93;
}
.%type S4 dram_rbuf_tbuf_ind_t{
__unnamed 0 111;
}
.%type S4 {
__unnamed 0 112;
value 0 90;
}
.%type S4 {
ov_ueng_addr 0:31:1 90;
ueng_addr 0:26:5 90;
ov_ref_count 0:25:1 90;
ref_count 0:21:4 90;
reserved 0:19:2 90;
buf_addr 0:5:14 90;
ov_buf_addr 0:4:1 90;
ov_ctx 0:3:1 90;
ctx 0:0:3 90;
}
.%type P3 114
.%type U1
.%type U4
.%type E4 {
POOL0 0;
POOL1 1;
POOL2 2;
POOL3 3;
POOL4 4;
POOL5 5;
POOL6 6;
POOL7 7;
}
.%type A16 115
.%type A8 115
.%type I4
.%type S4 {
__unnamed 0 121;
}
.%type S4 {
__unnamed 0 122;
value 0 115;
}
.%type S4 {
eop 0:31:1 115;
sop 0:30:1 115;
seg_count 0:24:6 115;
lw_offset 0:0:24 115;
}
.%scope global
.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c"
.%scope function scratch_ring_full _scratch_ring_full "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.h" 106 110 0 147 A0
.%scope end
.%scope function dl_sink_init _dl_sink_init "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 49 99 128 137 A0
.%scope end
.%scope function dl_sink _dl_sink "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 119 163 138 147 B1
.%var r_data 10 R 
.%liverange 0 A1 24:25 53:53 60:83 88:91 95:127 138:141 144:144
.%liverange 4 A0 53:54 144:144
.%liverange 8 B0 0:56 59:144 146:147
.%liverange 12 B1 0:147
.%scope end
.%scope end
.%scope file "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c"
.%scope function scratch_put_ring _scratch_put_ring "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 1938 2000 0 58 A0
.%scope block 1976 1996
.%var ind 18 R 
.%liverange 0 A0
.%scope end
.%var data 22 R 
.%liverange 0 A0
.%var address 13 R 
.%liverange 0 A0
.%var count 14 R 
.%liverange 0 A0
.%var sync 15 R 
.%liverange 0 A0
.%var sig_ptr 16 R 
.%liverange 0 A0
.%scope end
.%scope function scratch_get_ring _scratch_get_ring "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 2156 2218 0 0 A0
.%scope block 2194 2214
.%scope end
.%scope end
.%scope function cap_read _cap_read "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 6616 6741 0 0 A0
.%scope block 6679 6737
.%scope end
.%scope end
.%scope function cap_write _cap_write "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 7040 7166 0 35 A0
.%scope block 7104 7162
.%var ind 18 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%scope end
.%var data 22 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var address 14 R 
.%liverange 0 A1 0:19 28:29 128:132
.%liverange 0 A1 0:19 28:31 128:132
.%liverange 0 A1 0:19 28:33 128:132
.%var count 14 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var reflect_sig 56 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var sync 15 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var sig_ptr 16 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%scope end
.%scope function cap_fast_write _cap_fast_write "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 7766 7789 0 137 A0
.%var data 14 R 
.%liverange 0 A0
.%var cap_csr 57 R 
.%liverange 0 A0
.%scope end
.%scope function msf_write _msf_write "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 8230 8292 0 52 A0
.%scope block 8268 8288
.%var ind 18 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%scope end
.%var data 22 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var address 58 R 
.%liverange 0 A0 0:21 28:37 128:137
.%liverange 0 A0 0:21 28:39 128:137
.%liverange 0 A0 0:21 28:40 128:137
.%liverange 0 A0 0:21 28:41 128:137
.%liverange 0 A0 0:21 28:42 128:137
.%liverange 0 A0 0:21 28:44 128:137
.%liverange 0 A0 0:21 28:46 128:137
.%liverange 0 A0 0:21 28:48 128:137
.%liverange 0 A0 0:21 28:51 128:137
.%var count 14 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var sync 15 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var sig_ptr 16 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%scope end
.%scope function local_csr_read _local_csr_read "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 13139 13155 0 0 A0
.%scope end
.%scope function inp_state_test _inp_state_test "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 15392 15408 0 147 A0
.%var state_name 76 R 
.%liverange 0 A0
.%var result 17 R 
.%liverange 0 A0
.%scope end
.%scope end
.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c"
.%scope function scratch_ring_init _scratch_ring_init "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 40 87 28 35 B0
.%var ring_number 77 R 
.%liverange 0 A0
.%var ring_base 77 R 
.%liverange 0 A1 0:19 28:28 128:132
.%var ring_size 77 R 
.%liverange 0 A0
.%var ring_init 77 R 
.%liverange 0 $W0 29:33
.%var ring_head 77 R 
.%liverange 0 $W1 31:33
.%var ring_tail 77 R 
.%liverange 0 $W2 33:33
.%var ring_init_sig 78 R 
.%liverange 0 G3 30:34
.%var ring_head_sig 78 R 
.%liverange 0 G2 32:34
.%var ring_tail_sig 78 R 
.%liverange 0 G1 34:34
.%scope end
.%scope function scratch_ring_put_buffer _scratch_ring_put_buffer "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 200 215 53 58 B2
.%var ring_number 77 R 
.%liverange 0 A0
.%var data 80 R 
.%liverange 0 A0
.%liverange 4 A0
.%liverange 8 A0
.%liverange 12 A0
.%var ring_addr 84 R 
.%liverange 0 A3 0:147
.%var ring_signal 78 R 
.%liverange 0 G1
.%var packet 80 R 
.%liverange 0 $W0 54:55
.%liverange 4 $W1 55:55
.%liverange 8 $W2 0:55 57:147
.%liverange 12 $W3 0:55 58:147
.%scope end
.%scope end
.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c"
.%scope function spi4_rx_init _spi4_rx_init "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 109 159 36 52 B0
.%var addr 99 R 
.%liverange 0 A0
.%var rx_ctl 90 R 
.%liverange 0 $W0 37:37 39:42 44:44 46:46 48:48 51:51
.%var msf_rx_ctl_sig 93 R 
.%liverange 0 G1
.%scope end
.%scope function spi4_rx _spi4_rx "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 316 409 59 127 A3
.%var cur_mpacket_addr 113 R 
.%liverange 0 B0 0:95 98:147
.%var alloc_handle 87 R 
.%liverange 0 $R0 93:94
.%var rsw 101 R 
.%liverange 0 B1 79:81 89:100 104:125
.%liverange 4 A0
.%var rbuf_to_dram_sig 109 R 
.%liverange 0 G2 115:116
.%liverange 4 G3 115:116
.%var buf_alloc_sig 93 R 
.%liverange 0 G1 93:93
.%scope end
.%scope end
.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_rx_dl.c"
.%scope function main _main "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_rx_dl.c" 35 60 0 27 A0
.%scope end
.%scope end
.%var dlBufHandle 0 R 
.%liverange 0 A1 24:25 53:53 60:83 88:91 95:127 138:141 144:144
.%var dlNextBlock 5 R 
.%liverange 0 A0
.%var dlMeta 6 R 
.%liverange 0 A0
.%liverange 4 A2 0:147
.%liverange 8 A0
.%liverange 12 A0
.%liverange 16 A0
.%liverange 20 A0
.%liverange 24 A0
.%liverange 28 A0
.%scope end
+ucode_end