📄 spi4_rx_dl_uc.list
字号:
alu[b2, b0, AND, 7]
.66 F0010C0000 common_code
.%operands 0 0 0 -- -- -- -- a0 A0 -- --
.%line 207 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ rx_tfl.parts.me_no = __ME();
l_130#:
immed[a0, (((0 & 4294905855) | ((1 & 15) << 12)) & 65535), 0]
.67 F4400C0000 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 207 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
immed_w1[a0, (((0 & 4294905855) | ((1 & 15) << 12)) >> 16)]
.68 899000FE00 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 207 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu_shf[a0, a0, AND~, 31, <<7]
.69 8B90000E00 common_code
.%operands 0 0 0 a0 A0 b3 B3 a0 A0 -- --
.%line 207 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu_shf[a0, a0, OR, b3, <<7]
.70 89C0009E00 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 210 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ rx_tfl.parts.thd = ctx();
alu_shf[a0, a0, AND~, 7, <<4]
.71 8BC0000A00 common_code
.%operands 0 0 0 a0 A0 b2 B2 a0 A0 -- --
.%line 210 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu_shf[a0, a0, OR, b2, <<4]
.72 880000BC00 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 214 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ rx_tfl.parts.xfer_reg = __xfer_reg_number(&rsw);
alu_shf[a0, a0, AND~, 15, <<0]
.73 8A00008000 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 214 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu_shf[a0, a0, OR, (0 & 11), <<0]
.74 8B0009C200 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 221 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ msf_fast_write(rx_tfl_addr_and_val);
alu_shf[a0, 48, OR, a0, <<16]
.75 3D00048300 common_code
.%operands 0 1 0 a0 A0 -- -- -- -- -- --
.%line 221 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
msf[fast_wr, --, a0, 0, 1]
.76 E000000002 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 222 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ wait_for_all(&rx_complete_sig); // wait for an mpacket
ctx_arb[s1], all
.77 D01650B880 common_code
.%operands 0 0 1 rsw $R0 -- -- rsw $R0 -- --
.%line 338 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 1 89
/******/ if (rsw.w1.parts.err)
br_bclr[$0, 13, l_183#], defer[1]
.78 B000160000 common_code
.%operands 0 0 0 rsw $R0 -- -- rsw B1 -- --
.%line 333 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
/******/ rsw = _spi4_rx_get_mpacket();
alu[b1, --, B, $0]
.79 A070000001 common_code
.%operands 0 0 0 _dlBufHandle A1 -- -- -- -- -- --
.%line 340 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ if (dlBufHandle.value != 0)
alu[--, --, B, a1]
.80 D815600100 common_code
.%operands 0 0 2 -- -- -- -- -- -- -- --
.%line 340 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 2 85
beq[l_178#], defer[2]
.81 8480000506 common_code
.%operands 0 0 0 a6 A6 rsw B1 a0 A0 -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
/******/ msf_fast_write(val_and_addr);
alu_shf[a0, a6, AND, b1, >>8]
.82 AA000D1000 common_code
.%operands 0 0 0 a0 A0 -- -- address A0 -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
alu[a0, a0, OR, 68]
.83 C007181001 common_code
.%operands 0 0 0 _dlBufHandle A1 -- -- _sram_addr B4 -- --
.%line 722 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/ __asm ld_field[_sram_addr, 0111b, in_sram_addr]
ld_field_w_clr[b4, 0111, a1, <<0]
.84 0C00001320 common_code
.%operands 0 1 0 _sram_addr B4 -- -- -- -- -- --
.%line 731 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/ sram_enqueue((volatile void __declspec(sram) *)_sram_addr);
sram[enqueue, --, b4, 0]
.85 3D00048300 common_code
.%operands 0 1 0 address A0 -- -- -- -- -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ msf_fast_write(val_and_addr);
l_178#:
msf[fast_wr, --, a0, 0, 1]
.86 D810A00018 common_code
.%operands 0 0 2 -- -- -- -- -- -- -- --
.%line 348 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 2 66
/******/ dlMeta.bufferSize = 0;
br[l_130#], defer[2]
.87 F0000C0001 common_code
.%operands 0 0 0 -- -- -- -- _dlBufHandle A1 -- --
.%line 347 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
/******/ dlBufHandle.value = 0;
immed[a1, 0, <<0]
.88 8900201A02 common_code
.%operands 0 0 0 _dlMeta A2 b6 B6 _dlMeta A2 -- --
.%line 348 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
/******/ dlMeta.bufferSize = 0;
alu_shf[a2, a2, AND~, b6, <<16]
.89 D018800430 common_code
.%operands 0 0 0 rsw B1 -- -- rsw B1 -- --
.%line 353 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0 98
/******/ if (rsw.w1.parts.sop)
l_183#:
br_bclr[b1, 15, l_209#]
.90 A070000001 common_code
.%operands 0 0 0 _dlBufHandle A1 -- -- -- -- -- --
.%line 355 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ if (dlBufHandle.value == 0)
alu[--, --, B, a1]
.91 D818000101 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 355 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0 96
bne[l_207#]
.92 0B10001720 common_code
.%operands 2 1 0 address B5 -- -- -- -- alloc_handle $R0
.%line 657 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/ sram_dequeue((__declspec(sram_read_reg) void *) out_sram_addr, /* data to read */
sram[dequeue, $0, b5, 0], sig_done[s1]
.93 E000000002 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 363 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ wait_for_all(&buf_alloc_sig);
ctx_arb[s1], all
.94 A000160000 common_code
.%operands 0 0 0 alloc_handle $R0 -- -- _dlBufHandle A1 -- --
.%line 364 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ dlBufHandle = alloc_handle;
alu[a1, --, B, $0]
.95 D819000100 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 366 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0 100
/******/ if (dlBufHandle.value == 0)
beq[l_1136#]
.96 D81A100018 common_code
.%operands 0 0 1 -- -- -- -- -- -- -- --
.%line 373 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 1 104
/******/ cur_mpacket_addr = (__declspec(dram) unsigned char *)
l_207#:
br[l_214#], defer[1]
.97 C18E180201 common_code
.%operands 0 0 0 _dlBufHandle A1 -- -- cur_mpacket_addr B0 -- --
.%line 373 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
ld_field_w_clr[b0, 1110, a1, <<8]
.98 A070000001 common_code
.%operands 0 0 0 _dlBufHandle A1 -- -- -- -- -- --
.%line 376 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ else if (dlBufHandle.value == 0)
l_209#:
alu[--, --, B, a1]
.99 D81A000101 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 376 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0 104
bne[l_214#]
.100 8480000506 common_code
.%operands 0 0 0 a6 A6 rsw B1 a0 A0 -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ msf_fast_write(val_and_addr);
l_1136#:
alu_shf[a0, a6, AND, b1, >>8]
.101 AA000D1000 common_code
.%operands 0 0 0 a0 A0 -- -- address A0 -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu[a0, a0, OR, 68]
.102 3D00048300 common_code
.%operands 0 1 0 address A0 -- -- -- -- -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
msf[fast_wr, --, a0, 0, 1]
.103 D810800018 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0 66
br[l_130#]
.104 85800005FF common_code
.%operands 0 0 0 rsw B1 -- -- a0 A0 -- --
.%line 385 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ _spi4_rx_move_rbuf_to_dram(
l_214#:
alu_shf[a0, 127, AND, b1, >>24]
.105 C101100504 common_code
.%operands 0 0 0 rsw B1 -- -- a4 A4 -- --
.%line 385 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
ld_field_w_clr[a4, 0001, b1, >>16]
.106 8BA0081E00 common_code
.%operands 0 0 0 b7 B7 a0 A0 rbuf_addr A0 -- --
.%line 270 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ rbuf_addr = MSF_RBUF_BASE_ADDR + (in_rbuf_elem << 6);
alu_shf[a0, b7, OR, a0, <<6]
.107 8BB0088200 common_code
.%operands 0 0 0 rbuf_addr A0 -- -- a0 A0 -- --
.%line 275 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ indir.buf_addr = rbuf_addr;
alu_shf[a0, 0, OR, a0, <<5]
.108 AA0053FC00 common_code
.%operands 0 0 0 a0 A0 @b127 @B127 indir A5 -- --
.%line 278 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ indir.ov_ref_count = 1;
alu[a5, a0, OR, @b127]
.109 A0800C1C04 common_code
.%operands 0 0 0 a4 A4 -- -- a0 A0 -- --
.%line 279 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ indir.ref_count = ((in_size + 7) >> 3) - 1;
alu[a0, a4, +, 7]
.110 8030080100 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 279 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu_shf[a0, --, B, a0, >>3]
.111 AA800C0400 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 279 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu[a0, a0, -, 1]
.112 B4004C3C00 common_code
.%operands 0 0 0 a0 A0 -- -- b4 B4 -- --
.%line 279 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu[b4, a0, AND, 15]
.113 8AB0001205 common_code
.%operands 0 0 0 indir A5 b4 B4 a0 A0 -- --
.%line 279 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu_shf[a0, a5, OR, b4, <<21]
.114 6A2E000320 common_code
.%operands 4 32 0 cur_mpacket_addr B0 -- -- -- -- -- --
.%line 281 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
/******/ dram_rbuf_read_ind(in_dram_addr,
dram[rbuf_rd, --, b0, 0, 16], sig_done[s2], indirect_ref
.115 C101100500 common_code
.%operands 0 0 0 rsw B1 -- -- a0 A0 -- --
.%line 392 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
/******/ dlMeta.bufferSize += rsw.w1.parts.byte_count;
ld_field_w_clr[a0, 0001, b1, >>16]
.116 E00020000C common_code
.%operands 0 0 2 -- -- -- -- -- -- -- --
.%line 395 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 2
/******/ __wait_for_all(&rbuf_to_dram_sig);
ctx_arb[s3, s2], all, defer[2]
.117 9100480102 common_code
.%operands 0 0 0 _dlMeta A2 -- -- b4 B4 -- --
.%line 392 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
/******/ dlMeta.bufferSize += rsw.w1.parts.byte_count;
alu_shf[b4, --, B, a2, >>16]
.118 B0C0401000 common_code
.%operands 0 0 0 b4 B4 a0 A0 b4 B4 -- --
.%line 392 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
alu[b4, b4, +, a0]
.119 8480000506 common_code
.%operands 0 0 0 a6 A6 rsw B1 a0 A0 -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
/******/ msf_fast_write(val_and_addr);
alu_shf[a0, a6, AND, b1, >>8]
.120 AA000D1000 common_code
.%operands 0 0 0 a0 A0 -- -- address A0 -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
alu[a0, a0, OR, 68]
.121 3D00048300 common_code
.%operands 0 1 0 address A0 -- -- -- -- -- --
.%line 86 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0
msf[fast_wr, --, a0, 0, 1]
.122 D01FD4042F common_code
.%operands 0 0 1 rsw B1 -- -- rsw B1 -- --
.%line 400 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 1 127
/******/ if (rsw.w1.parts.eop)
br_bset[b1, 14, l_246#], defer[1]
.123 C10C001202 common_code
.%operands 0 0 0 _dlMeta A2 b4 B4 _dlMeta A2 -- --
.%line 392 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
/******/ dlMeta.bufferSize += rsw.w1.parts.byte_count;
ld_field[a2, 1100, b4, <<16]
.124 D810A00018 common_code
.%operands 0 0 2 -- -- -- -- -- -- -- --
.%line 406 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 2 66
/******/ cur_mpacket_addr += rsw.w1.parts.byte_count;
br[l_130#], defer[2]
.125 C101100500 common_code
.%operands 0 0 0 rsw B1 -- -- a0 A0 -- --
.%line 406 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
ld_field_w_clr[a0, 0001, b1, >>16]
.126 B080000000 common_code
.%operands 0 0 0 a0 A0 cur_mpacket_addr B0 cur_mpacket_addr B0 -- --
.%line 406 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 0 0
alu[b0, a0, +, b0]
.127 E8000C0003 common_code
.%operands 0 0 0 a3 A3 -- -- a3 A3 -- --
.%line 409 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_rx.c" 1 0 0 A3
/******/ }
l_246#:
rtn[a3]
_dl_sink_init#:
.128 FC04400000 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 51 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0
/******/ if (ctx() == 0)
local_csr_rd[active_ctx_sts]
.129 F000000300 common_code
.%operands 0 0 0 -- -- -- -- b0 B0 -- --
.%line 51 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
immed[b0, 0, <<0]
.130 B440000307 common_code
.%operands 0 0 0 b0 B0 -- -- b0 B0 -- --
.%line 51 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0
alu[b0, b0, AND, 7]
.131 D822400101 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 51 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0 137
bne[l_869#]
.132 D807200018 common_code
.%operands 0 0 2 -- -- -- -- -- -- -- --
.%line 56 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 2 28
/******/ scratch_ring_init(
br[_scratch_ring_init#], defer[2]
.133 F0010C0001 common_code
.%operands 0 0 0 -- -- -- -- ring_base A1 -- --
.%line 56 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
immed[a1, 4096, <<0]
.134 F000000387 common_code
.%operands 0 0 0 -- -- -- -- b0 B0 -- --
.%line 56 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
load_addr[b0, l_1143#]
.%import_expr common_code 135 <17:10:0> 1 _rx_ring_ready_sig &r 0 + 128 |
.135 A0300C0000 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 62 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0
/******/ cap_fast_write(
l_1143#:
alu[--, --, B, ((&remote(_rx_ring_ready_sig,1) + 0) | 128)]
.136 320001031C common_code
.%operands 4 1 0 -- -- -- -- -- -- -- --
.%line 62 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
cap[fast_wr_alu, 0, interthread_sig]
.137 E8000C0000 common_code
.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
.%line 99 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0 0 A0
/******/ }
l_869#:
rtn[a0]
_dl_sink#:
.138 D823408214 common_code
.%operands 0 0 0 -- -- -- -- -- -- -- --
.%line 108 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.h" 1 0 141
/******/ return inp_state_test(inp_state_scr_ring0_full +
br_inp_state[scr_ring0_status, l_276#]
.139 D824100018 common_code
.%operands 0 0 1 -- -- -- -- -- -- -- --
.%line 108 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.h" 1 1 144
br[l_274#], defer[1]
.140 8100080102 common_code
.%operands 0 0 0 _dlMeta A2 -- -- r_data A0 -- --
.%line 155 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
/******/ r_data.length = dlMeta.bufferSize;
alu_shf[a0, --, B, a2, >>16]
.141 C007180001 common_code
.%operands 0 0 0 _dlBufHandle A1 -- -- _sram_addr B0 -- --
.%line 722 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/ __asm ld_field[_sram_addr, 0111b, in_sram_addr]
l_276#:
ld_field_w_clr[b0, 0111, a1, <<0]
.142 0C00000320 common_code
.%operands 0 1 0 _sram_addr B0 -- -- -- -- -- --
.%line 731 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/ sram_enqueue((volatile void __declspec(sram) *)_sram_addr);
sram[enqueue, --, b0, 0]
.143 E800000700 common_code
.%operands 0 0 0 b1 B1 -- -- b1 B1 -- --
.%line 149 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0 0 B1
/******/ return;
rtn[b1]
.144 D80D600018 common_code
.%operands 0 0 2 -- -- -- -- -- -- -- --
.%line 157 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 2 53
/******/ scratch_ring_put_buffer(
l_274#:
br[_scratch_ring_put_buffer#], defer[2]
.145 C003180002 common_code
.%operands 0 0 0 _dlMeta A2 -- -- r_data B0 -- --
.%line 156 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
/******/ r_data.offset = dlMeta.offset;
ld_field_w_clr[b0, 0011, a2, >>0]
.146 F000000B93 common_code
.%operands 0 0 0 -- -- -- -- b2 B2 -- --
.%line 156 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
load_addr[b2, l_1144#]
.147 E800000700 common_code
.%operands 0 0 0 b1 B1 -- -- b1 B1 -- --
.%line 163 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0 0 B1
/******/ }
l_1144#:
rtn[b1]
.%type S4 {
__unnamed 0 1;
}
.%type S4 {
__unnamed 0 2;
value 0 3;
}
.%type S4 {
eop 0:31:1 3;
sop 0:30:1 3;
seg_count 0:24:6 3;
lw_offset 0:0:24 3;
}
.%type U4
.%type E4 {
POOL0 0;
POOL1 1;
POOL2 2;
POOL3 3;
POOL4 4;
POOL5 5;
POOL6 6;
POOL7 7;
}
.%type I4
.%type S32 {
__unnamed 0 7;
value 0 9;
}
.%type S32 {
bufferNext 0 0;
bufferSize 4 8;
offset 6 8;
packetSize 8:16:16 3;
freeListId 8:12:4 3;
rxStat 8:8:4 3;
headerType 8:0:8 3;
inputPort 12 8;
outputPort 14 8;
nextHopId 16:16:16 3;
fabricPort 16:8:8 3;
reserved 16:4:4 3;
nhidType 16:0:4 3;
colorId 20:28:4 3;
reserved1 20:24:4 3;
flowId 20:0:24 3;
classId 24 8;
reserved2 26 8;
packetNext 28 3;
}
.%type U2
.%type A32 3
.%type S16 ring_data_t{
handle 0 0;
length 4 3;
offset 8 3;
sequence 12 3;
}
.%type P2 12
.%type U4
.%type P1 12
.%type U4
.%type E4 {
sig_done 0;
ctx_swap 1;
}
.%type P2 17
.%type I4
.%type S4 scratch_read_write_ind_t{
__unnamed 0 19;
}
.%type S4 {
__unnamed 0 20;
value 0 14;
}
.%type S4 {
ov_ueng_addr 0:31:1 14;
ueng_addr 0:26:5 14;
ov_ref_count 0:25:1 14;
ref_count 0:21:4 14;
reserved 0:12:9 14;
xadd 0:5:7 14;
ov_xadd 0:4:1 14;
ov_ctx 0:3:1 14;
ctx 0:0:3 14;
}
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