spi4_tx_dl_uc.list

ixp2400的一个小程序

csr_scratch_ring_base_15 18672;
csr_scratch_ring_head_15 18676;
csr_scratch_ring_tail_15 18680;
csr_product_id 18944;
csr_misc_control 18948;
csr_perf_counter_control 18952;
csr_ixp_reset_0 18956;
csr_ixp_reset_1 18960;
csr_clock_control 18964;
csr_strap_options 18968;
}
.%type P2 11
.%type P2 11
.%type P2 16
.%type P2 11
.%type P2 11
.%type S4 hash_ind_t{
__unnamed 0 63;
}
.%type S4 {
__unnamed 0 64;
value 0 13;
}
.%type S4 {
ov_ueng_addr 0:31:1 13;
ueng_addr 0:26:5 13;
ov_hash_count 0:25:1 13;
reserved1 0:23:2 13;
hash_count 0:21:2 13;
reserved2 0:12:9 13;
xadd 0:5:7 13;
ov_xadd 0:4:1 13;
ov_ctx 0:3:1 13;
ctx 0:0:3 13;
}
.%type P2 11
.%type E4 {
token_none 0;
token_0 1;
token_1 2;
token_0_1 3;
}
.%type S4 generic_ind_t{
dram_rw 0 49;
sram_rw 0 33;
sram_ring 0 17;
pci_rw 0 33;
sram_atomic 0 36;
sram_enqueue 0 42;
sram_dequeue 0 45;
scratch_rw 0 17;
scratch_ring 0 17;
sram_rd_qdesc 0 17;
sram_journal 0 17;
cap_rw 0 17;
msf_rw 0 17;
reflect_rw 0 17;
hash 0 62;
dram_rbuf_tbuf 0 52;
scratch_atomic 0 23;
sram_csr_rw 0 23;
cap_csr_rw 0 23;
value 0 13;
}
.%type E4 {
local_csr_ustore_address 0;
local_csr_ustore_data_lower 1;
local_csr_ustore_data_upper 2;
local_csr_ustore_error_status 3;
local_csr_alu_out 4;
local_csr_ctx_arb_cntl 5;
local_csr_ctx_enables 6;
local_csr_cc_enable 7;
local_csr_csr_ctx_pointer 8;
local_csr_indirect_ctx_sts 16;
local_csr_active_ctx_sts 17;
local_csr_indirect_ctx_sig_events 18;
local_csr_active_ctx_sig_events 19;
local_csr_indirect_ctx_wakeup_events 20;
local_csr_active_ctx_wakeup_events 21;
local_csr_indirect_ctx_future_count 22;
local_csr_active_ctx_future_count 23;
local_csr_byte_index 28;
local_csr_indirect_lm_addr_0 24;
local_csr_active_lm_addr_0 25;
local_csr_indirect_lm_addr_1 26;
local_csr_active_lm_addr_1 27;
local_csr_indirect_lm_addr_0_byte_index 56;
local_csr_active_lm_addr_0_byte_index 57;
local_csr_indirect_lm_addr_1_byte_index 58;
local_csr_active_lm_addr_1_byte_index 59;
local_csr_t_index_byte_index 61;
local_csr_t_index 29;
local_csr_indirect_future_count_signal 30;
local_csr_active_future_count_signal 31;
local_csr_nn_put 32;
local_csr_nn_get 33;
local_csr_timestamp_low 48;
local_csr_timestamp_high 49;
local_csr_next_neighbor_signal 64;
local_csr_prev_neighbor_signal 65;
local_csr_same_me_signal 66;
local_csr_crc_remainder 80;
local_csr_profile_count 81;
local_csr_pseudo_random_number 82;
local_csr_datapath_signature 83;
local_csr_datapath_signature_enable 84;
local_csr_debug 85;
local_csr_local_csr_status 96;
local_csr_reserved 255;
}
.%type E4 {
bytes_0_3 0;
bytes_0_2 1;
bytes_0_1 2;
byte_0 3;
bytes_1_3 4;
bytes_2_3 5;
byte_3 6;
}
.%type S4 cam_lookup_t{
__unnamed 0 71;
}
.%type S4 {
__unnamed 0 72;
value 0 13;
}
.%type S4 {
zeros1 0:12:20 13;
state 0:8:4 13;
hit 0:7:1 13;
entry_num 0:3:4 13;
zeros2 0:0:3 13;
}
.%type I8
.%type E4 {
kill 0;
voluntary 1;
bpt 2;
}
.%type E4 {
inp_state_nn_empty 0;
inp_state_nn_full 1;
inp_state_scr_ring0_status 2;
inp_state_scr_ring1_status 3;
inp_state_scr_ring2_status 4;
inp_state_scr_ring3_status 5;
inp_state_scr_ring4_status 6;
inp_state_scr_ring5_status 7;
inp_state_scr_ring6_status 8;
inp_state_scr_ring7_status 9;
inp_state_scr_ring8_status 10;
inp_state_scr_ring9_status 11;
inp_state_scr_ring10_status 12;
inp_state_scr_ring11_status 13;
inp_state_scr_ring0_full 2;
inp_state_scr_ring1_full 3;
inp_state_scr_ring2_full 4;
inp_state_scr_ring3_full 5;
inp_state_scr_ring4_full 6;
inp_state_scr_ring5_full 7;
inp_state_scr_ring6_full 8;
inp_state_scr_ring7_full 9;
inp_state_scr_ring8_full 10;
inp_state_scr_ring9_full 11;
inp_state_scr_ring10_full 12;
inp_state_scr_ring11_full 13;
inp_state_fci_not_empty 14;
inp_state_fci_full 15;
inp_state_fcififo_empty 14;
inp_state_fcififo_full 15;
}
.%type U4
.%type I4
.%type P2 79
.%type S16 ring_data_t{
handle 0 80;
length 4 76;
offset 8 76;
sequence 12 76;
}
.%type S4 {
__unnamed 0 81;
}
.%type S4 {
__unnamed 0 82;
value 0 76;
}
.%type S4 {
eop 0:31:1 76;
sop 0:30:1 76;
seg_count 0:24:6 76;
lw_offset 0:0:24 76;
}
.%type P1 84
.%type U4
.%type S4 {
__unnamed 0 86;
}
.%type S4 {
__unnamed 0 87;
value 0 88;
}
.%type S4 {
eop 0:31:1 88;
sop 0:30:1 88;
seg_count 0:24:6 88;
lw_offset 0:0:24 88;
}
.%type U4
.%type E4 {
POOL0 0;
POOL1 1;
POOL2 2;
POOL3 3;
POOL4 4;
POOL5 5;
POOL6 6;
POOL7 7;
}
.%type I4
.%type S32 {
__unnamed 0 92;
value 0 94;
}
.%type S32 {
bufferNext 0 85;
bufferSize 4 93;
offset 6 93;
packetSize 8:16:16 88;
freeListId 8:12:4 88;
rxStat 8:8:4 88;
headerType 8:0:8 88;
inputPort 12 93;
outputPort 14 93;
nextHopId 16:16:16 88;
fabricPort 16:8:8 88;
reserved 16:4:4 88;
nhidType 16:0:4 88;
colorId 20:28:4 88;
reserved1 20:24:4 88;
flowId 20:0:24 88;
classId 24 93;
reserved2 26 93;
packetNext 28 88;
}
.%type U2
.%type A32 88
.%type S20 s_tx_state{
sop 0 88;
eop 4 88;
cur_mpacket_addr 8 96;
remaining_length 12 88;
cur_buf_handle 16 85;
}
.%type P3 97
.%type U1
.%type P3 99
.%type U4
.%type P2 101
.%type S8 {
even 0 90;
odd 4 90;
}
.%type S4 dram_rbuf_tbuf_ind_t{
__unnamed 0 103;
}
.%type S4 {
__unnamed 0 104;
value 0 88;
}
.%type S4 {
ov_ueng_addr 0:31:1 88;
ueng_addr 0:26:5 88;
ov_ref_count 0:25:1 88;
ref_count 0:21:4 88;
reserved 0:19:2 88;
buf_addr 0:5:14 88;
ov_buf_addr 0:4:1 88;
ov_ctx 0:3:1 88;
ctx 0:0:3 88;
}
.%type S8 s_spi4_tcw{
control_word 0 106;
reserved 4 88;
}
.%type S4 {
parts 0 107;
whole 0 88;
}
.%type S4 {
payload_length 0:24:8 88;
prepend_offset 0:21:3 88;
prepend_length 0:16:5 88;
payload_offset 0:13:3 88;
res1 0:12:1 88;
skip 0:11:1 88;
err 0:10:1 88;
sop 0:9:1 88;
eop 0:8:1 88;
m32ci 0:7:1 88;
res2 0:5:2 88;
channel 0:0:5 88;
}
.%type P2 88
.%type P2 99
.%type U4
.%type E4 {
POOL0 0;
POOL1 1;
POOL2 2;
POOL3 3;
POOL4 4;
POOL5 5;
POOL6 6;
POOL7 7;
}
.%type A16 110
.%type A8 110
.%type I4
.%type S4 {
__unnamed 0 116;
}
.%type S4 {
__unnamed 0 117;
value 0 110;
}
.%type S4 {
eop 0:31:1 110;
sop 0:30:1 110;
seg_count 0:24:6 110;
lw_offset 0:0:24 110;
}
.%scope global
.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c"
.%scope function dl_source_init _dl_source_init "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 183 202 26 31 A0
.%scope end
.%scope function dl_source _dl_source "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 221 246 49 54 B0
.%var r_data 9 T sram$tls+0 16
.%scope end
.%scope end
.%scope file "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c"
.%scope function scratch_put_ring _scratch_put_ring "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 1938 2000 0 0 A0
.%scope block 1976 1996
.%scope end
.%scope end
.%scope function scratch_get_ring _scratch_get_ring "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 2156 2218 0 48 A0
.%scope block 2194 2214
.%var ind 17 R 
.%liverange 0 A0
.%scope end
.%var data 10 R 
.%liverange 0 A0
.%var address 12 R 
.%liverange 0 A0
.%var count 13 R 
.%liverange 0 A0
.%var sync 14 R 
.%liverange 0 A0
.%var sig_ptr 15 R 
.%liverange 0 A0
.%scope end
.%scope function cap_read _cap_read "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 6616 6741 0 0 A0
.%scope block 6679 6737
.%scope end
.%scope end
.%scope function cap_write _cap_write "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 7040 7166 0 0 A0
.%scope block 7104 7162
.%scope end
.%scope end
.%scope function msf_write _msf_write "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 8230 8292 0 41 A0
.%scope block 8268 8288
.%var ind 17 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%scope end
.%var data 21 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var address 57 R 
.%liverange 0 B0 0:19 32:32
.%liverange 0 B0 0:19 32:34
.%liverange 0 B0 0:19 32:36
.%liverange 0 B0 0:19 32:37
.%liverange 0 B0 0:19 32:38
.%liverange 0 B0 0:19 32:40
.%var count 13 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var sync 14 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%var sig_ptr 15 R 
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%liverange 0 A0
.%scope end
.%scope function local_csr_read _local_csr_read "G:\IXA_SDK_3.5\MicroengineC\src\intrinsic.c" 13139 13155 0 0 A0
.%scope end
.%scope end
.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c"
.%scope function scratch_ring_get_buffer _scratch_ring_get_buffer "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 158 174 42 48 A0
.%var ring_number 76 R 
.%liverange 0 A0
.%var data 78 R 
.%liverange 0 A0
.%var ring_addr 83 R 
.%liverange 0 A1 0:22 24:130
.%var ring_signal 77 R 
.%liverange 0 G1
.%var packet 79 R 
.%liverange 0 $R0 43:43
.%liverange 4 $R1 43:44
.%liverange 8 $R2 43:46
.%liverange 12 $R3 43:47
.%scope end
.%scope end
.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c"
.%scope function spi4_tx_init _spi4_tx_init "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 90 120 32 41 A0
.%var addr 109 R 
.%liverange 0 A0
.%var tx_ctl 88 R 
.%liverange 0 $W0 0:19 32:32 34:34 36:38 40:40
.%var msf_tx_ctl_sig 90 R 
.%liverange 0 G1
.%scope end
.%scope function spi4_tx _spi4_tx "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 408 495 55 130 A0
.%var next_tbuf_elem 88 R 
.%liverange 0 B2 42:54 56:130
.%var last_tx_seq 88 R 
.%liverange 0 A3 42:54 58:67 72:111 114:130
.%var tbufs_in_flight 88 R 
.%liverange 0 A2 42:54 57:130
.%var dram_to_tbuf_sig 101 R 
.%liverange 0 G2 100:114
.%liverange 4 G3 100:114
.%var cur_state 95 R 
.%liverange 0 A1 86:116
.%liverange 4 A4 59:72 88:88 90:130
.%liverange 8 A0
.%liverange 12 B1 91:115
.%liverange 16 A0 85:128
.%scope end
.%scope end
.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c"
.%scope function main _main "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c" 36 59 0 25 A0
.%scope end
.%scope end
.%var tx_ring_ready_sig 0 R 
.%liverange 0 G2 0:21 26:30 32:41
.%var dlBufHandle 1 R 
.%liverange 0 A5 0:22 24:41 54:73 75:130
.%var dlMeta 5 R 
.%liverange 0 A0
.%liverange 4 A0 75:80
.%liverange 8 A0
.%liverange 12 A0
.%liverange 16 A0
.%liverange 20 A0
.%liverange 24 A0
.%liverange 28 A0
.%scope end
+ucode_end