spi4_tx_dl_uc.list

ixp2400的一个小程序

+version:  10/31/2000
+switches:

+comp_ver Version:       3.5
+Release:       1.4
+Build Number:  8.0.71.3 (v1.4)
+Build Date:    Nov 21 2003 16:15:19

.%bigendian

.cpu_version 0x00000002 16 255
.%num_contexts 8


.%local_mem0_mode rel
.%local_mem1_mode rel
.%init_nn_mode neighbor

.%local_mem dram$tls dram 0 16
.%local_mem sram3$tls sram3 0
.%local_mem sram2$tls sram2 0
.%local_mem sram1$tls sram1 0
.%local_mem sram$tls sram 128
.%local_mem scratch$tls scratch 0
.%init_reg A5 0x0
.%init_reg B3 0x0
.%init_reg B4 0x0
.%init_reg B5 0x0
.%init_reg A9 0x400
.%init_reg B11 0x1000
.%init_reg A13 0x1800
.%init_reg A12 0x2000
.%init_reg B8 0x60
.%init_reg A11 0x9C
.%init_reg B10 0x98
.%init_reg A10 0x94
.%init_reg B9 0x90
.%init_reg A8 0x4
.%init_reg @A118 sram$tls &v 112 +
.%init_reg @A102 sram$tls &v 96 +
.%init_reg @A86 sram$tls &v 80 +
.%init_reg @A70 sram$tls &v 64 +
.%init_reg @A54 sram$tls &v 48 +
.%init_reg @A38 sram$tls &v 32 +
.%init_reg @A22 sram$tls &v 16 +
.%init_reg @B127 0x2000010
.%init_reg @A6 sram$tls &v 0 +
:_dl_source#	49
:_dl_source_init#	26
:_main#	0
:_scratch_ring_get_buffer#	42
:_spi4_tx#	55
:_spi4_tx_init#	32
:l_100#	15
:l_102#	19
:l_104#	23
:l_1045#	31
:l_1055#	21
:l_1056#	23
:l_1057#	25
:l_1058#	51
:l_1059#	76
:l_111#	59
:l_112#	61
:l_153#	67
:l_154#	68
:l_155#	72
:l_156#	74
:l_161#	81
:l_163#	89
:l_164#	91
:l_230#	111
:l_231#	112
:l_232#	114
:start#	0
*a0 gpr_a_rel 00
*a1 gpr_a_rel 01
*a2 gpr_a_rel 02
*a3 gpr_a_rel 03
*a4 gpr_a_rel 04
*a5 gpr_a_rel 05
*a6 gpr_a_rel 06
*a7 gpr_a_rel 07
*a8 gpr_a_rel 08
*a9 gpr_a_rel 09
*a10 gpr_a_rel 0A
*a11 gpr_a_rel 0B
*a12 gpr_a_rel 0C
*a13 gpr_a_rel 0D
*a14 gpr_a_rel 0E
*a15 gpr_a_rel 0F
*b0 gpr_b_rel 00
*b1 gpr_b_rel 01
*b2 gpr_b_rel 02
*b3 gpr_b_rel 03
*b4 gpr_b_rel 04
*b5 gpr_b_rel 05
*b6 gpr_b_rel 06
*b7 gpr_b_rel 07
*b8 gpr_b_rel 08
*b9 gpr_b_rel 09
*b10 gpr_b_rel 0A
*b11 gpr_b_rel 0B
*b12 gpr_b_rel 0C
*b13 gpr_b_rel 0D
*b14 gpr_b_rel 0E
*b15 gpr_b_rel 0F
*$0 sram_rel 000 1 both 0 0
*$1 sram_rel 001 1 both 0 0
*$2 sram_rel 002 1 both 0 0
*$3 sram_rel 003 1 both 0 0
*$4 sram_rel 004 1 both 0 0
*$5 sram_rel 005 1 both 0 0
*$6 sram_rel 006 1 both 0 0
*$7 sram_rel 007 1 both 0 0
*$8 sram_rel 008 1 both 0 0
*$9 sram_rel 009 1 both 0 0
*$10 sram_rel 00A 1 both 0 0
*$11 sram_rel 00B 1 both 0 0
*$12 sram_rel 00C 1 both 0 0
*$13 sram_rel 00D 1 both 0 0
*$14 sram_rel 00E 1 both 0 0
*$15 sram_rel 00F 1 both 0 0
*$$0 dram_rel 000 1 both 0 0
*$$1 dram_rel 001 1 both 0 0
*$$2 dram_rel 002 1 both 0 0
*$$3 dram_rel 003 1 both 0 0
*$$4 dram_rel 004 1 both 0 0
*$$5 dram_rel 005 1 both 0 0
*$$6 dram_rel 006 1 both 0 0
*$$7 dram_rel 007 1 both 0 0
*$$8 dram_rel 008 1 both 0 0
*$$9 dram_rel 009 1 both 0 0
*$$10 dram_rel 00A 1 both 0 0
*$$11 dram_rel 00B 1 both 0 0
*$$12 dram_rel 00C 1 both 0 0
*$$13 dram_rel 00D 1 both 0 0
*$$14 dram_rel 00E 1 both 0 0
*$$15 dram_rel 00F 1 both 0 0
*n$0 neighbor_rel 000
*n$1 neighbor_rel 001
*n$2 neighbor_rel 002
*n$3 neighbor_rel 003
*n$4 neighbor_rel 004
*n$5 neighbor_rel 005
*n$6 neighbor_rel 006
*n$7 neighbor_rel 007
*n$8 neighbor_rel 008
*n$9 neighbor_rel 009
*n$10 neighbor_rel 00A
*n$11 neighbor_rel 00B
*n$12 neighbor_rel 00C
*n$13 neighbor_rel 00D
*n$14 neighbor_rel 00E
*n$15 neighbor_rel 00F
*@b127 gpr_b_abs FF
*_tx_ring_ready_sig signal   2 1
_main#:
.0 FC04400000 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0
/******/  	if (ctx() == 0 && __ME() == 0)

	local_csr_rd[active_ctx_sts]
.1 F000000300 common_code
	.%operands 0 0 0 -- -- -- -- cgt.6 B0 -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 0 0
	immed[b0, 0, <<0]
.2 A440000307 common_code
	.%operands 0 0 0 cgt.6 B0 -- -- a0 A0 -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0
	alu[a0, b0, AND, 7]
.3 D804C00101 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0 19
	bne[l_102#]
.4 843000013F common_code
	.%operands 0 0 0 cgt.6 B0 -- -- a0 A0 -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0
	alu_shf[a0, 31, AND, b0, >>3]
.5 D804C00101 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0 19
	bne[l_102#]
.6 F0000C0180 common_code
	.%operands 0 0 0 -- -- -- -- in_data $W0 -- --
	.%line 543 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  	in_data[0] = 0;

	immed[$0, 0, <<0]
.7 F0000C0181 common_code
	.%operands 0 0 0 -- -- -- -- in_data $W1 -- --
	.%line 544 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  	in_data[1] = 0;

	immed[$1, 0, <<0]
.8 0116002E20 common_code
	.%operands 1 4 2 sram_addr B11 -- -- -- -- in_data $W0
	.%line 555 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 2
/******/  	sram_write(&in_data[0], (volatile void __declspec(sram) *)sram_addr, 4, ctx_swap, &sig_buf);

	sram[write, $0, b11, 0, 4], ctx_swap[s1], defer[2]
.9 F0000C0182 common_code
	.%operands 0 0 0 -- -- -- -- in_data $W2 -- --
	.%line 545 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 0 0
/******/  	in_data[2] = 0;

	immed[$2, 0, <<0]
.10 F0000C0183 common_code
	.%operands 0 0 0 -- -- -- -- in_data $W3 -- --
	.%line 546 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 0 0
/******/  	in_data[3] = 0;

	immed[$3, 0, <<0]
.11 0F12048109 common_code
	.%operands 2 2 1 address A9 -- -- -- -- out_data $R0
	.%line 558 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 1
/******/  	sram_read_qdesc_tail(&out_data[0], (volatile void __declspec(sram) *)sram_qa_addr, 2, ctx_swap, &sig_enq);

	sram[rd_qdesc_tail, $0, a9, 0, 2], ctx_swap[s1], defer[1]
.12 F000400300 common_code
	.%operands 0 0 0 -- -- -- -- sram_addr B0 -- --
	.%line 565 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 0 0
/******/  	sram_addr = s_base_lw;

	immed[b0, 1024, <<0]
.13 0F00008309 common_code
	.%operands 0 1 0 address A9 -- -- -- -- -- --
	.%line 559 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  	sram_read_qdesc_other((volatile void __declspec(sram) *)sram_qa_addr);

	sram[rd_qdesc_other, --, a9, 0]
.14 F0001D0000 common_code
	.%operands 0 0 0 -- -- -- -- _buf_fc_cnt A0 -- --
	.%line 561 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  	_buf_fc_cnt = NUM_BUFFERS;

	immed[a0, 320, <<0]
.15 0C00000320 common_code
	.%operands 0 1 0 sram_addr B0 -- -- -- -- -- --
	.%line 580 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  		__asm sram[enqueue, --, sram_addr, 0]

l_100#:
	sram[enqueue, --, b0, 0]
.16 AA800C0400 common_code
	.%operands 0 0 0 _buf_fc_cnt A0 -- -- _buf_fc_cnt A0 -- --
	.%line 583 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  		_buf_fc_cnt = _buf_fc_cnt - 1;

	alu[a0, a0, -, 1]
.17 D803D00101 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 574 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 1 15
/******/  	while (_buf_fc_cnt)

	bne[l_100#], defer[1]
.18 B0C0000308 common_code
	.%operands 0 0 0 sram_addr B0 -- -- sram_addr B0 -- --
	.%line 582 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 0 0
/******/  		sram_addr = sram_addr + s_size_lw;

	alu[b0, b0, +, 8]
.19 D808100018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 45 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c" 1 1 32
/******/  	spi4_tx_init();

l_102#:
	br[_spi4_tx_init#], defer[1]
.20 F0000C5400 common_code
	.%operands 0 0 0 -- -- -- -- a0 A0 -- --
	.%line 45 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c" 0 0
	load_addr[a0, l_1055#]
.21 D806900018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 48 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c" 1 1 26
/******/  	dl_source_init();

l_1055#:
	br[_dl_source_init#], defer[1]
.22 F0000C5C00 common_code
	.%operands 0 0 0 -- -- -- -- a0 A0 -- --
	.%line 48 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c" 0 0
	load_addr[a0, l_1056#]
.23 D80DD00018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 57 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c" 1 1 55
/******/  		spi4_tx();

l_104#:
	br[_spi4_tx#], defer[1]
.24 F0000C6400 common_code
	.%operands 0 0 0 -- -- -- -- a0 A0 -- --
	.%line 57 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c" 0 0
	load_addr[a0, l_1057#]
.25 D805C00018 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 57 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\spi4_tx_dl.c" 1 0 23
l_1057#:
	br[l_104#]
_dl_source_init#:
.26 FC04400000 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 185 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0
/******/  	if (ctx() == 0)

	local_csr_rd[active_ctx_sts]
.27 F000000300 common_code
	.%operands 0 0 0 -- -- -- -- b0 B0 -- --
	.%line 185 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
	immed[b0, 0, <<0]
.28 B440000307 common_code
	.%operands 0 0 0 b0 B0 -- -- b0 B0 -- --
	.%line 185 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0
	alu[b0, b0, AND, 7]
.29 D807C00101 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 185 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0 31
	bne[l_1045#]
.30 E000000004 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 198 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0
/******/  		wait_for_all(&tx_ring_ready_sig);

	ctx_arb[s2], all
.31 E8000C0000 common_code
	.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
	.%line 202 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0 0 A0
/******/  }

l_1045#:
	rtn[a0]
_spi4_tx_init#:
.32 3D10008108 common_code
	.%operands 1 1 1 address A8 -- -- -- -- tx_ctl $W0
	.%line 100 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 1
/******/  	msf_write(&tx_ctl, addr, 1, ctx_swap, &msf_tx_ctl_sig);

	msf[write, $0, a8, 0, 1], ctx_swap[s1], defer[1]
.33 F4000C2180 common_code
	.%operands 0 0 0 -- -- -- -- tx_ctl $W0 -- --
	.%line 98 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 0 0
/******/  	tx_ctl = TX_CONTROL_VAL;

	immed[$0, 8, <<16]
.34 3D10002520 common_code
	.%operands 1 1 1 address B9 -- -- -- -- tx_ctl $W0
	.%line 106 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 1
/******/  	msf_write(&tx_ctl,addr,1,ctx_swap,&msf_tx_ctl_sig);

	msf[write, $0, b9, 0, 1], ctx_swap[s1], defer[1]
.35 F0000CC580 common_code
	.%operands 0 0 0 -- -- -- -- tx_ctl $W0 -- --
	.%line 104 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 0 0
/******/  	tx_ctl= TX_UP_CONTROL_VAL;

	immed[$0, 49, <<0]
.36 3D1000800A common_code
	.%operands 1 1 0 address A10 -- -- -- -- tx_ctl $W0
	.%line 109 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0
/******/  	msf_write(&tx_ctl,addr,1,ctx_swap,&msf_tx_ctl_sig);

	msf[write, $0, a10, 0, 1], ctx_swap[s1]
.37 3D10002820 common_code
	.%operands 1 1 0 address B10 -- -- -- -- tx_ctl $W0
	.%line 112 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0
/******/  	msf_write(&tx_ctl,addr,1,ctx_swap,&msf_tx_ctl_sig);

	msf[write, $0, b10, 0, 1], ctx_swap[s1]
.38 3D1000800B common_code
	.%operands 1 1 0 address A11 -- -- -- -- tx_ctl $W0
	.%line 115 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0
/******/  	msf_write(&tx_ctl,addr,1,ctx_swap,&msf_tx_ctl_sig);

	msf[write, $0, a11, 0, 1], ctx_swap[s1]
.39 F4010C2180 common_code
	.%operands 0 0 0 -- -- -- -- tx_ctl $W0 -- --
	.%line 118 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0
/******/  	tx_ctl=TX_CONTROL_VAL_SECOND;

	immed[$0, 4104, <<16]
.40 3D10008008 common_code
	.%operands 1 1 0 address A8 -- -- -- -- tx_ctl $W0
	.%line 119 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0
/******/  	msf_write(&tx_ctl,addr,1,ctx_swap,&msf_tx_ctl_sig);

	msf[write, $0, a8, 0, 1], ctx_swap[s1]
.41 E8000C0000 common_code
	.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
	.%line 120 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0 0 A0
/******/  }

	rtn[a0]
_scratch_ring_get_buffer#:
.42 1916008008 common_code
	.%operands 2 4 0 ring_addr A8 -- -- -- -- packet $R0
	.%line 167 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 1 0
/******/  	scratch_get_ring(&packet,

	scratch[get, $0, a8, 0, 4], ctx_swap[s1]
.43 A018060000 common_code
	.%operands 0 0 0 packet $R0 -- -- $0 $W0 -- --
	.%line 173 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 1 0
/******/  	*data = packet;

	alu[$0, --, B, $0]
.44 A018160400 common_code
	.%operands 0 0 0 packet $R1 -- -- $1 $W1 -- --
	.%line 173 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 1 0
	alu[$1, --, B, $1]
.45 0116008206 common_code
	.%operands 1 4 2 a6 A6 -- -- -- -- $0 $W0
	.%line 173 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 1 2
	sram[write, $0, a6, 0, 4], ctx_swap[s1], defer[2]
.46 A018260800 common_code
	.%operands 0 0 0 packet $R2 -- -- $2 $W2 -- --
	.%line 173 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 0 0
	alu[$2, --, B, $2]
.47 A018360C00 common_code
	.%operands 0 0 0 packet $R3 -- -- $3 $W3 -- --
	.%line 173 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 0 0
	alu[$3, --, B, $3]
.48 E8000C0000 common_code
	.%operands 0 0 0 a0 A0 -- -- a0 A0 -- --
	.%line 174 "G:\IXA_SDK_3.5\modify_c_hw3\scratch_rings.c" 1 0 0 A0
/******/  }

	rtn[a0]
_dl_source#:
.49 D80A900018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 237 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 1 42
/******/  	scratch_ring_get_buffer(

	br[_scratch_ring_get_buffer#], defer[1]
.50 F0000CCC00 common_code
	.%operands 0 0 0 -- -- -- -- a0 A0 -- --
	.%line 237 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
	load_addr[a0, l_1058#]
.51 0012008006 common_code
	.%operands 2 2 0 a6 A6 -- -- -- -- cgt.10 $R0
	.%line 240 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 0
/******/  	dlBufHandle       = r_data.handle;

l_1058#:
	sram[read, $0, a6, 0, 2], ctx_swap[s1]
.52 E800200300 common_code
	.%operands 0 0 2 b0 B0 -- -- b0 B0 -- --
	.%line 246 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 1 2 0 B0
/******/  }

	rtn[b0], defer[2]
.53 A000560000 common_code
	.%operands 0 0 0 cgt.10 $R0 -- -- _dlBufHandle A5 -- --
	.%line 240 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
/******/  	dlBufHandle       = r_data.handle;

	alu[a5, --, B, $0]
.54 8100020600 common_code
	.%operands 0 0 0 cgt.10 $R1 -- -- _dlMeta A0 -- --
	.%line 241 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\dl_source.c" 0 0
/******/  	dlMeta.bufferSize = r_data.length;

	alu_shf[a0, --, B, $1, <<16]
_spi4_tx#:
.55 F000000B00 common_code
	.%operands 0 0 0 -- -- -- -- next_tbuf_elem B2 -- --
	.%line 430 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0
/******/  	next_tbuf_elem  = 0;

	immed[b2, 0, <<0]
.56 F0000C0002 common_code
	.%operands 0 0 0 -- -- -- -- tbufs_in_flight A2 -- --
	.%line 431 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0
/******/  	tbufs_in_flight = 0;

	immed[a2, 0, <<0]
.57 F0000C0003 common_code
	.%operands 0 0 0 -- -- -- -- last_tx_seq A3 -- --
	.%line 432 "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 1 0
/******/  	last_tx_seq     = 0;

	immed[a3, 0, <<0]
.58 F0000C0404 common_code