rx.h

ixp2400的一个小程序

//  Copyright (C) 2002-2003 Intel Corporation, All Rights Reserved.
//  Permission is hereby granted to merge this program code with 
//  other program material to create a derivative work.  This 
//  derivative work may be distributed in compiled object form only.
//  Any other publication of this program, in any form, without the 
//  explicit permission of the copyright holder is prohibited.
//
//  Send questions and comments to [e-mail], 
//  [e-mail]

//-------------------------------------------------------------------
// rx.h - Chapter 5
// Common values and datastructures  for the receive reassembly  
// task.  Uses dispatcher to send packets to the processing code.
//

#ifndef RX_H
#define RX_H


//-------------------------------------------------------------------
// Bit positions within the MSF receive control CSR 
/* msf_rx_control for spi4
#define RX_EN_SPHY_BITPOS					30
#define RBUF_ELE_SIZE_0_BITPOS				2
#define RBUF_PARTITION_BITPOS				0
*/
//msf_rx_control for spi3
#define RX_EN_SPHY_BITPOS					28
#define RBUF_ELE_SIZE_0_BITPOS              2
#define RX_MPHY_LEVEL2                      14
#define RX_MPHY_EN					        19
#define RX_MPHY_MODE					    18
#define RX_WIDTH                     		20
#define RX_MPHY_POLL_MODE                   17
#define RX_MODE 						    22
//-------------------------------------------------------------------
// Bit positions within the SPHY4 receive status word
//#define RSW_SPHY4_ADDR_BITPOS				0
#define RSW_SPHY4_TYPE_BITPOS				7
#define RSW_SPHY4_NULL_BITPOS				9
#define RSW_SPHY4_ERRORS_BITPOS				13
#define RSW_SPHY4_EOP_BITPOS				14
#define RSW_SPHY4_SOP_BITPOS				15
#define RSW_SPHY4_BYTECOUNT_BITPOS			16
#define RSW_SPHY4_BYTECOUNT_MASK			0xff
#define RSW_SPHY4_ELEMENT_BITPOS			24
#define RSW_SPHY4_ELEMENT_MASK				0x7f

//-------------------------------------------------------------------
// MSF memory map
#define MSF_RX_CONTROL_ADDR					0x0
#define MSF_HWM_CONTROL_ADDR				0x24
#define MST_HWM_CONTROL__RBUF_S_HWM__MASK   0xFFFFFFCF
#define MST_HWM_CONTROL__RBUF_S_HWM__00     0x00000000
#define MST_HWM_CONTROL__RBUF_S_HWM__01     0x00000010
#define MST_HWM_CONTROL__RBUF_S_HWM__10     0x00000020
#define MST_HWM_CONTROL__RBUF_S_HWM__11     0x00000030
#define MSF_RX_THREAD_FREELIST_0_ADDR		0x30
#define MSF_RX_PORT_MAP_ADDR				0x40
#define MSF_RBUF_ELEMENT_DONE_ADDR			0x44
//#define MSF_RX_CALENDAR_LENGTH_ADDR			0x48
//#define MSF_TX_CALENDAR_LENGTH_ADDR			0x70
#define MSF_RX_MPHY_POLL_LIMIT				0x48
#define MSF_TX_MPHY_POLL_LIMIT				0x70
//#define MSF_TRAIN_DATA_ADDR					0xA0
#define MSF_Rx_FIFO_Control_0				0xA0
//#define MSF_TRAIN_DATA__RSTAT_EN            0x00000002
#define MSF_TRAIN_DATA__RSTAT_EN            0x0000f93b

#define MSF_RBUF_BASE_ADDR					0x2000    
//add by rock the rx_up_control 0 address  
#define MSF_RX_UP_CONTROL_0_ADDR	     0x0080
#define MSF_RX_UP_CONTROL_1_ADDR	     0x0084
#define MSF_RX_UP_CONTROL_2_ADDR	     0x0088
#define MSF_RX_UP_CONTROL_3_ADDR	     0x008c
//-----------------------------------------------------------------\
//define the rx_up_control regester bit
#define RX_UP_CPMODE    4
#define RX_UP_PPMODE	 5
#define RX_UP_DETIME     0
//-------------------------------------------------------------------
// MicroC data structures
#ifdef MICRO_C

//-------------------------------------------------------------------
// The SPI4 receive status words
typedef struct s_spi4_rsw 
{
	// The first status word
	union
	{
		struct 
		{
			unsigned int	rprot		: 1,
							element		: 7,
							byte_count	: 8,
							sop			: 1,
							eop			: 1,
							err			: 1,
							len_err		: 1,
							par_err		: 1,
							abort_err	: 1,
							null		: 1,
							type		: 1,
							addr		: 8;

		} parts;
		unsigned int whole;
	} w1;

	// The second status word
	union
	{
		unsigned int whole;
	} w2;
} spi4_rsw_t;

#endif // MICRO_C


#endif // RX_H