spi4_tx.dbg

ixp2400的一个小程序

.%scope file "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c"
.%scope function ixp_buf_free _ixp_buf_free "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 703 732
.%arg in_sram_addr 0 in_sram_addr_723_V$412
.%arg POOL_ID 4 POOL_ID_723_V$41a
.%arg d_base 3 d_base_723_V$41b
.%arg d_size 3 d_size_723_V$41c
.%arg s_base 3 s_base_723_V$41d
.%arg s_size 3 s_size_723_V$41e
.%var _BUF_FREE_CHNL_NUM 3 _BUF_FREE_CHNL_NUM_723 LIX
.%var _sram_addr 3 _sram_addr_723 LIX
.%scope end
.%var tx_ring_ready_sig 5 _tx_ring_ready_sig SEX
.%var dlBufHandle 0 _dlBufHandle SEX
.%var dlMeta 6 _dlMeta SEX
.%var tx_state 10 _tx_state SIX
.%scope function Dl_BufFree _Dl_BufFree "G:\IXA_SDK_3.5\src\library\microblocks_library\microc\dl_buf.c" 115 125
.%arg bufHandle 0 bufHandle_733_V$421
.%arg freeList 4 freeList_733_V$429
.%arg dBase 3 dBase_733_V$42a
.%arg dSize 3 dSize_733_V$42b
.%arg sBase 3 sBase_733_V$42c
.%arg sSize 3 sSize_733_V$42d
.%scope end
.%scope function Dl_BufGetData _Dl_BufGetData "G:\IXA_SDK_3.5\src\library\microblocks_library\microc\dl_buf.c" 191 208
.%arg bufHandle 0 bufHandle_735_V$42e
.%var sdramOffset 3 sdramOffset_735 LIX
.%scope end
.%scope function Dl_BufDrop _Dl_BufDrop "G:\IXA_SDK_3.5\src\library\microblocks_library\microc\dl_buf.c" 263 266
.%arg bufHandle 0 bufHandle_737_V$438
.%scope end
.%scope function _spi4_tx_move_dram_to_tbuf __spi4_tx_move_dram_to_tbuf "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 149 178
.%arg in_tbuf_elem 3 in_tbuf_elem_750_V$440
.%arg in_dram_addr 13 in_dram_addr_750_V$441
.%arg in_size 3 in_size_750_V$442
.%arg in_dram_sig 15 in_dram_sig_750_V$443
.%var indir 17 indir_750 LIX
.%var tbuf_addr 3 tbuf_addr_750 LIX
.%scope end
.%scope function _spi4_tx_validate_tbuf __spi4_tx_validate_tbuf "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 202 231
.%arg in_tbuf_elem 3 in_tbuf_elem_751_V$452
.%arg in_sop 3 in_sop_751_V$453
.%arg in_eop 3 in_eop_751_V$454
.%arg in_size 3 in_size_751_V$455
.%var tbuf_control 20 tbuf_control_751 LIX
.%var tbuf_control_wr 20 tbuf_control_wr_751 LIW
.%var msf_sig 5 msf_sig_751 LIX
.%scope end
.%scope function _spi4_tx_update_tbufs_in_flight __spi4_tx_update_tbufs_in_flight "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 263 297
.%arg io_tbufs_in_flight 23 io_tbufs_in_flight_752_V$479
.%arg io_last_tx_seq 23 io_last_tx_seq_752_V$47a
.%var cur_tx_seq 3 cur_tx_seq_752 LIX
.%var cur_tx_seq_rd 3 cur_tx_seq_rd_752 LIR
.%var tbufs_used 3 tbufs_used_752 LIX
.%var msf_sig 5 msf_sig_752 LIX
.%scope end
.%scope function _spi4_tx_get_and_update_state __spi4_tx_get_and_update_state "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 333 386
.%arg in_next_tbuf_elem 3 in_next_tbuf_elem_755_V$47f
.%var ret_state 10 ret_state_755 LIX
.%scope end
.%scope function spi4_tx_init _spi4_tx_init "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 90 120
.%var addr 24 addr_749 LIX
.%var tx_ctl 3 tx_ctl_749 LIW
.%var msf_tx_ctl_sig 5 msf_tx_ctl_sig_749 LIX
.%scope end
.%scope function spi4_tx _spi4_tx "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 408 495
.%var next_tbuf_elem 3 next_tbuf_elem_761 LIX
.%var last_tx_seq 3 last_tx_seq_761 LIX
.%var tbufs_in_flight 3 tbufs_in_flight_761 LIX
.%var dram_to_tbuf_sig 16 dram_to_tbuf_sig_761 LIX
.%var cur_state 10 cur_state_761 LIX
.%scope end
.%scope function exit _exit "G:\IXA_SDK_3.5\modify_c_hw3\spi4_tx.c" 497 500
.%arg code 3 code_766_V$4b0
.%scope end
.%type S4 {
__unnamed 0 1;
}
.%type S4 {
__unnamed 0 2;
value 0 3;
}
.%type S4 {
eop 0:31:1 3;
sop 0:30:1 3;
seg_count 0:24:6 3;
lw_offset 0:0:24 3;
}
.%type U4
.%type E4 {
POOL0 0;
POOL1 1;
POOL2 2;
POOL3 3;
POOL4 4;
POOL5 5;
POOL6 6;
POOL7 7;
}
.%type I4
.%type S32 {
__unnamed 0 7;
value 0 9;
}
.%type S32 {
bufferNext 0 0;
bufferSize 4 8;
offset 6 8;
packetSize 8:16:16 3;
freeListId 8:12:4 3;
rxStat 8:8:4 3;
headerType 8:0:8 3;
inputPort 12 8;
outputPort 14 8;
nextHopId 16:16:16 3;
fabricPort 16:8:8 3;
reserved 16:4:4 3;
nhidType 16:0:4 3;
colorId 20:28:4 3;
reserved1 20:24:4 3;
flowId 20:0:24 3;
classId 24 8;
reserved2 26 8;
packetNext 28 3;
}
.%type U2
.%type A32 3
.%type S20 s_tx_state{
sop 0 3;
eop 4 3;
cur_mpacket_addr 8 11;
remaining_length 12 3;
cur_buf_handle 16 0;
}
.%type P3 12
.%type U1
.%type P3 14
.%type U4
.%type P2 16
.%type S8 {
even 0 5;
odd 4 5;
}
.%type S4 dram_rbuf_tbuf_ind_t{
__unnamed 0 18;
}
.%type S4 {
__unnamed 0 19;
value 0 3;
}
.%type S4 {
ov_ueng_addr 0:31:1 3;
ueng_addr 0:26:5 3;
ov_ref_count 0:25:1 3;
ref_count 0:21:4 3;
reserved 0:19:2 3;
buf_addr 0:5:14 3;
ov_buf_addr 0:4:1 3;
ov_ctx 0:3:1 3;
ctx 0:0:3 3;
}
.%type S8 s_spi4_tcw{
control_word 0 21;
reserved 4 3;
}
.%type S4 {
parts 0 22;
whole 0 3;
}
.%type S4 {
payload_length 0:24:8 3;
prepend_offset 0:21:3 3;
prepend_length 0:16:5 3;
payload_offset 0:13:3 3;
res1 0:12:1 3;
skip 0:11:1 3;
err 0:10:1 3;
sop 0:9:1 3;
eop 0:8:1 3;
m32ci 0:7:1 3;
res2 0:5:2 3;
channel 0:0:5 3;
}
.%type P2 3
.%type P2 14