count_us.list

ixp2400的一个小程序

+version:  10/31/2000
+switches:

+comp_ver Version:       3.5
+Release:       1.4
+Build Number:  8.0.71.3 (v1.4)
+Build Date:    Nov 21 2003 16:15:19

.%bigendian

.cpu_version 0x00000002 16 255
.%num_contexts 8


.%local_mem0_mode rel
.%local_mem1_mode rel
.%init_nn_mode neighbor

.%local_mem dram$tls dram 0 16
.%local_mem sram3$tls sram3 0
.%local_mem sram2$tls sram2 0
.%local_mem sram1$tls sram1 0
.%local_mem sram$tls sram 320
.%local_mem scratch$tls scratch 0
.sig remote _tx_ring_ready_sig
.%init_reg A8 0x4
.%init_reg A9 0x8
.%init_reg B9 0x4
.%init_reg A10 0x8
.%init_reg B14 0x400
.%init_reg B13 0xFFFFFFFC
.%init_reg A14 0xFFFFFFFF
.%init_reg @A117 sram$tls &v 280 +
.%init_reg @A101 sram$tls &v 240 +
.%init_reg @A85 sram$tls &v 200 +
.%init_reg @A69 sram$tls &v 160 +
.%init_reg @A53 sram$tls &v 120 +
.%init_reg @A37 sram$tls &v 80 +
.%init_reg @A21 sram$tls &v 40 +
.%init_reg @A95 0x800
.%init_reg @A127 0x100000
.%init_reg @A111 0xFFFF
.%init_reg @B127 0xFFFFFFFF
.%init_reg @A5 sram$tls &v 0 +
:__shl_64#	74
:_dl_sink#	241
:_dl_sink_init#	463
:_dl_source#	456
:_dl_source_init#	50
:_ethernet_add_header#	256
:_ethernet_strip_header#	180
:_ethernet_validate#	197
:_main#	0
:_scratch_ring_get_buffer#	232
:_scratch_ring_init#	63
:_scratch_ring_put_buffer#	90
:_tos#	363
:_tos_init#	56
:_ua_get_64_dram#	97
:_ua_set_64_dram#	124
:l_100#	16
:l_102#	20
:l_105#	26
:l_115#	47
:l_168#	202
:l_169#	204
:l_174#	228
:l_175#	230
:l_210#	394
:l_229#	418
:l_251#	140
:l_2559#	80
:l_2561#	88
:l_2562#	89
:l_265#	156
:l_278#	171
:l_279#	173
:l_315#	114
:l_3230#	473
:l_3237#	55
:l_3239#	213
:l_3240#	219
:l_3246#	189
:l_3274#	22
:l_3275#	24
:l_3276#	26
:l_3277#	28
:l_3278#	32
:l_3279#	36
:l_3280#	40
:l_3281#	42
:l_3282#	46
:l_3283#	255
:l_3284#	278
:l_3285#	295
:l_3286#	314
:l_3287#	334
:l_3288#	351
:l_3289#	370
:l_3290#	377
:l_3291#	384
:l_3292#	424
:l_3293#	430
:l_3294#	437
:l_3295#	440
:l_3296#	446
:l_3297#	452
:l_3298#	458
:l_3299#	470
:l_346#	120
:l_348#	123
:l_360#	264
:l_372#	246
:l_389#	252
:l_391#	249
:start#	0
*a0 gpr_a_rel 00
*a1 gpr_a_rel 01
*a2 gpr_a_rel 02
*a3 gpr_a_rel 03
*a4 gpr_a_rel 04
*a5 gpr_a_rel 05
*a6 gpr_a_rel 06
*a7 gpr_a_rel 07
*a8 gpr_a_rel 08
*a9 gpr_a_rel 09
*a10 gpr_a_rel 0A
*a11 gpr_a_rel 0B
*a12 gpr_a_rel 0C
*a13 gpr_a_rel 0D
*a14 gpr_a_rel 0E
*a15 gpr_a_rel 0F
*b0 gpr_b_rel 00
*b1 gpr_b_rel 01
*b2 gpr_b_rel 02
*b3 gpr_b_rel 03
*b4 gpr_b_rel 04
*b5 gpr_b_rel 05
*b6 gpr_b_rel 06
*b7 gpr_b_rel 07
*b8 gpr_b_rel 08
*b9 gpr_b_rel 09
*b10 gpr_b_rel 0A
*b11 gpr_b_rel 0B
*b12 gpr_b_rel 0C
*b13 gpr_b_rel 0D
*b14 gpr_b_rel 0E
*b15 gpr_b_rel 0F
*$0 sram_rel 000 1 both 0 0
*$1 sram_rel 001 1 both 0 0
*$2 sram_rel 002 1 both 0 0
*$3 sram_rel 003 1 both 0 0
*$4 sram_rel 004 1 both 0 0
*$5 sram_rel 005 1 both 0 0
*$6 sram_rel 006 1 both 0 0
*$7 sram_rel 007 1 both 0 0
*$8 sram_rel 008 1 both 0 0
*$9 sram_rel 009 1 both 0 0
*$10 sram_rel 00A 1 both 0 0
*$11 sram_rel 00B 1 both 0 0
*$12 sram_rel 00C 1 both 0 0
*$13 sram_rel 00D 1 both 0 0
*$14 sram_rel 00E 1 both 0 0
*$15 sram_rel 00F 1 both 0 0
*$$0 dram_rel 000 1 both 0 0
*$$1 dram_rel 001 1 both 0 0
*$$2 dram_rel 002 1 both 0 0
*$$3 dram_rel 003 1 both 0 0
*$$4 dram_rel 004 1 both 0 0
*$$5 dram_rel 005 1 both 0 0
*$$6 dram_rel 006 1 both 0 0
*$$7 dram_rel 007 1 both 0 0
*$$8 dram_rel 008 1 both 0 0
*$$9 dram_rel 009 1 both 0 0
*$$10 dram_rel 00A 1 both 0 0
*$$11 dram_rel 00B 1 both 0 0
*$$12 dram_rel 00C 1 both 0 0
*$$13 dram_rel 00D 1 both 0 0
*$$14 dram_rel 00E 1 both 0 0
*$$15 dram_rel 00F 1 both 0 0
*n$0 neighbor_rel 000
*n$1 neighbor_rel 001
*n$2 neighbor_rel 002
*n$3 neighbor_rel 003
*n$4 neighbor_rel 004
*n$5 neighbor_rel 005
*n$6 neighbor_rel 006
*n$7 neighbor_rel 007
*n$8 neighbor_rel 008
*n$9 neighbor_rel 009
*n$10 neighbor_rel 00A
*n$11 neighbor_rel 00B
*n$12 neighbor_rel 00C
*n$13 neighbor_rel 00D
*n$14 neighbor_rel 00E
*n$15 neighbor_rel 00F
*@b127 gpr_b_abs FF
*@a111 gpr_a_abs 6F
*@a127 gpr_a_abs 7F
*@a95 gpr_a_abs 5F
*_rx_ring_ready_sig signal   2 1
_main#:
.0 FC04400000 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0
/******/  	if (ctx() == 0 && __ME() == 0)

	local_csr_rd[active_ctx_sts]
.1 F000000300 common_code
	.%operands 0 0 0 -- -- -- -- cgt.408 B0 -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 0 0
	immed[b0, 0, <<0]
.2 A440000307 common_code
	.%operands 0 0 0 cgt.408 B0 -- -- a0 A0 -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0
	alu[a0, b0, AND, 7]
.3 D805000101 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0 20
	bne[l_102#]
.4 843000013F common_code
	.%operands 0 0 0 cgt.408 B0 -- -- a0 A0 -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0
	alu_shf[a0, 31, AND, b0, >>3]
.5 D805000101 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 46 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\system_init.h" 1 0 20
	bne[l_102#]
.6 F0000C0180 common_code
	.%operands 0 0 0 -- -- -- -- in_data $W0 -- --
	.%line 543 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  	in_data[0] = 0;

	immed[$0, 0, <<0]
.7 F0000C0181 common_code
	.%operands 0 0 0 -- -- -- -- in_data $W1 -- --
	.%line 544 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  	in_data[1] = 0;

	immed[$1, 0, <<0]
.8 F001000300 common_code
	.%operands 0 0 0 -- -- -- -- sram_addr B0 -- --
	.%line 551 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  		sram_addr = s_base;

	immed[b0, 4096, <<0]
.9 0116000220 common_code
	.%operands 1 4 2 sram_addr B0 -- -- -- -- in_data $W0
	.%line 555 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 2
/******/  	sram_write(&in_data[0], (volatile void __declspec(sram) *)sram_addr, 4, ctx_swap, &sig_buf);

	sram[write, $0, b0, 0, 4], ctx_swap[s1], defer[2]
.10 F0000C0182 common_code
	.%operands 0 0 0 -- -- -- -- in_data $W2 -- --
	.%line 545 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 0 0
/******/  	in_data[2] = 0;

	immed[$2, 0, <<0]
.11 F0000C0183 common_code
	.%operands 0 0 0 -- -- -- -- in_data $W3 -- --
	.%line 546 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 0 0
/******/  	in_data[3] = 0;

	immed[$3, 0, <<0]
.12 0F12043920 common_code
	.%operands 2 2 1 address B14 -- -- -- -- out_data $R0
	.%line 558 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 1
/******/  	sram_read_qdesc_tail(&out_data[0], (volatile void __declspec(sram) *)sram_qa_addr, 2, ctx_swap, &sig_enq);

	sram[rd_qdesc_tail, $0, b14, 0, 2], ctx_swap[s1], defer[1]
.13 F000400300 common_code
	.%operands 0 0 0 -- -- -- -- sram_addr B0 -- --
	.%line 565 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 0 0
/******/  	sram_addr = s_base_lw;

	immed[b0, 1024, <<0]
.14 0F00003B20 common_code
	.%operands 0 1 0 address B14 -- -- -- -- -- --
	.%line 559 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  	sram_read_qdesc_other((volatile void __declspec(sram) *)sram_qa_addr);

	sram[rd_qdesc_other, --, b14, 0]
.15 F0001D0000 common_code
	.%operands 0 0 0 -- -- -- -- _buf_fc_cnt A0 -- --
	.%line 561 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  	_buf_fc_cnt = NUM_BUFFERS;

	immed[a0, 320, <<0]
.16 0C00000320 common_code
	.%operands 0 1 0 sram_addr B0 -- -- -- -- -- --
	.%line 580 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  		__asm sram[enqueue, --, sram_addr, 0]

l_100#:
	sram[enqueue, --, b0, 0]
.17 AA800C0400 common_code
	.%operands 0 0 0 _buf_fc_cnt A0 -- -- _buf_fc_cnt A0 -- --
	.%line 583 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 0
/******/  		_buf_fc_cnt = _buf_fc_cnt - 1;

	alu[a0, a0, -, 1]
.18 D804100101 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 574 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 1 1 16
/******/  	while (_buf_fc_cnt)

	bne[l_100#], defer[1]
.19 B0C0000308 common_code
	.%operands 0 0 0 sram_addr B0 -- -- sram_addr B0 -- --
	.%line 582 "G:\IXA_SDK_3.5\src\library\dataplane_library\microC\ixp_buf.c" 0 0
/******/  		sram_addr = sram_addr + s_size_lw;

	alu[b0, b0, +, 8]
.20 D873D00018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 50 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 1 1 463
/******/  	dl_sink_init();

l_102#:
	br[_dl_sink_init#], defer[1]
.21 F000000316 common_code
	.%operands 0 0 0 -- -- -- -- b0 B0 -- --
	.%line 50 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 0 0
	load_addr[b0, l_3274#]
.22 D80E100018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 56 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 1 1 56
/******/  	tos_init();

l_3274#:
	br[_tos_init#], defer[1]
.23 F000000318 common_code
	.%operands 0 0 0 -- -- -- -- b0 B0 -- --
	.%line 56 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 0 0
	load_addr[b0, l_3275#]
.24 D80C900018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 58 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 1 1 50
/******/  	dl_source_init();

l_3275#:
	br[_dl_source_init#], defer[1]
.25 F0000C6800 common_code
	.%operands 0 0 0 -- -- -- -- a0 A0 -- --
	.%line 58 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 0 0
	load_addr[a0, l_3276#]
.26 D872100018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 66 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 1 1 456
/******/  		dl_source();

l_105#:
	br[_dl_source#], defer[1]
.27 F00000031C common_code
	.%operands 0 0 0 -- -- -- -- b0 B0 -- --
	.%line 66 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 0 0
	load_addr[b0, l_3277#]
.28 A070000003 common_code
	.%operands 0 0 0 _dlBufHandle A3 -- -- -- -- -- --
	.%line 68 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 1 0
/******/  		if (dlBufHandle.value == 0)

l_3277#:
	alu[--, --, B, a3]
.29 D806800100 common_code
	.%operands 0 0 0 -- -- -- -- -- -- -- --
	.%line 68 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 1 0 26
	beq[l_105#]
.30 D831500018 common_code
	.%operands 0 0 1 -- -- -- -- -- -- -- --
	.%line 80 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 1 1 197
/******/  		ethernet_validate();

	br[_ethernet_validate#], defer[1]
.31 F000000320 common_code
	.%operands 0 0 0 -- -- -- -- b0 B0 -- --
	.%line 80 "G:\IXA_SDK_3.5\modify_c_hw3\dispatch_loop\count_dl.c" 0 0