traffic_tb.v

交通灯的简单控制

//--------------------------------------------------------------------------------------------------
//
// Title       : traffic_tb
// Design      : traffic
// Author      : 番茄花园
// Company     : 番茄花园
//
//-------------------------------------------------------------------------------------------------
//
// File        : traffic_TB.v
// Generated   : Sun Nov 23 22:43:24 2008
// From        : traffic_TB_settings.txt
// By          : tb_verilog.pl ver. ver 1.2s
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

`timescale 1ms / 1ms  
`define clk_cycle 500
module traffic_tb;

 
//Internal signals declarations:
reg clk;
reg enable;
wire [3:0]control_1;
wire [3:0]control_2;
wire [7:0]time_1;
wire [7:0]time_2;

 always #`clk_cycle clk=~clk;

// Unit Under Test port map
	

initial
	
	//$monitor($realtime,,"ps %h %h %h %h %h %h ",clk,enable,control_1,control_2,time_1,time_2);
	begin 
		clk=0;
		enable=1;
		#(2*`clk_cycle) enable=0;
		#(5*`clk_cycle) enable=1;
		#(100*`clk_cycle) enable=0;
		#(2*`clk_cycle) enable=1;  
		#(60*`clk_cycle) enable=0; 
		#(200*`clk_cycle) enable=1;
		#(300*`clk_cycle) $stop;
	end
		
	
	traffic UUT (
		.clk(clk),
		.enable(enable),
		.control_1(control_1),
		.control_2(control_2),
		.time_1(time_1),
		.time_2(time_2));
endmodule